Regarding ADC error

[Kye-Hyun Park]

Posted on November 27, 2017 at 09:22

Dear all.

I measured ACD input increasing the voltage by 10mVdc. but, there are non-nonlinear points.

As the datasheet, ED and EL are +-1.5LSB and +_2LSB. It seems that my measurement result is bigger than them.

Could you please explain how to reduce the error?

Thank you in advance.

Vref : 3.3V

ADC clock : 72Mhz / 2 = 36Mhz

1 LSB : 3.3V / 4096 = 0.805664063

ADC channel : Fast channel ADC1 3channel

Sampling mode : Single-ended

Sampling time : ADC_SampleTime_7Cycles5

[AvaTar]

Posted on November 27, 2017 at 10:34

Have you checked that your test conditions (electrical and software settings like sample time) match those stated in the datasheet you cited ?

[Kye-Hyun Park]

Posted on November 28, 2017 at 01:26

I think below my condition was satisfied with those test condition on the table.

1. ADC clock freq : 36Mhz <= 72Mhz
2. Sampling freq : 2.57Msps <= 5Msps
   • ADC clock = 36Mhz
   • Tconv = 7.5+12.5 = 20 ADC clock cycles
   • Sampling freq. = 20 / 36*10^6 = 555.55ns; 1.8Msps
3. Vdda = Vref+ = 3.3V

[AvaTar]

Posted on November 28, 2017 at 08:16

The PCB design / layout has a significant influence, as have the tolerence and impedance of your (reference) input voltage source.

If you think some STM32 MCUs have a problem with the ADC peripheral, better discuss it with a ST FAE.

Most people here, like me, are users, and need to rely on the same documentation as you.

And the ST people present here are rarely hardware experts.

[Kye-Hyun Park]

Posted on November 28, 2017 at 12:39

Thank you for your comment. I'll discover the possible causes you mentioned.