Problem with stm32f745 work

[kitty7c6]

After the firmwared (or power off-on) and after the reset the same program takes a different amount of time in ticks. Find it in my oun code. Then tried to create code in Cube and check it - same thing. Then I checked clocking settings and frequency - it was same and after power off-on and after reset (HSE 8MHz, Sys 216M). Then I checked systic interruption systic (setting for 1ms), and it always was 1ms.

What to do and why it can be?

For example the simplest program:

volatile uint32_t *DWT_CONTROL = (uint32_t *)0xE0001000;

volatile uint32_t *DWT_CYCCNT = (uint32_t *)0xE0001004; 

volatile uint32_t *DEMCR = (uint32_t *)0xE000EDFC; 

volatile unsigned int *DWT_LAR   = (volatile unsigned int *)0xE0001FB0;

uint32_t Mcounter, count;

main()

{

 *DWT_LAR = 0xC5ACCE55; // unlock (CM7)

 // enable the use DWT

*DEMCR = *DEMCR | 0x01000000;

// Reset cycle counter

*DWT_CYCCNT = 0; 

// enable cycle counter

*DWT_CONTROL = *DWT_CONTROL | 1 ;

SystemClock_Config();

while(1)

{

u8 i=0;

Mcounter=*DWT_CYCCNT;

i =1;

count=*DWT_CYCCNT-Mcounter;

float op_time=count/216.0f;// count/F_CPU

SendToUart(count);

}

}

count after power off-on = 0;

count after reset = 34 ticks;

[kitty7c6]

Problem is solved, I use Icache and ART

static void SetSysClock(void)

{

 uint32_t PLLM = 8<< RCC_PLLCFGR_PLLM_Pos;

 uint32_t PLLN = 432 << RCC_PLLCFGR_PLLN_Pos;

 uint32_t PLLP = 0 << RCC_PLLCFGR_PLLP_Pos;

 uint32_t PLLQ = 9 << RCC_PLLCFGR_PLLQ_Pos;

 /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

 SCB_EnableICache();

 FLASH->ACR |= FLASH_ACR_LATENCY_7WS;  

 FLASH->ACR |= FLASH_ACR_ARTEN;  

 /* Select regulator voltage output Scale 1 mode, EnableOverDriveMode */

 PWR->CR1 |= (PWR_CR1_VOS_0 | PWR_CR1_VOS_1) | PWR_CR1_ODEN;

 /* Enable HSE */

 RCC->CR |= ((uint32_t)RCC_CR_HSEON); 

 /* Wait till HSE is ready */

 while((RCC->CR & RCC_CR_HSERDY)!=RCC_CR_HSERDY){} 

 /*RCC_PLL_ConfigDomain_SYS*/

 RCC->PLLCFGR &=~ RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLQ; //clear mask 

 RCC->PLLCFGR = RCC_PLLCFGR_PLLSRC_HSE | PLLM | PLLN | PLLP | PLLQ; //set mask 

 RCC->CR |= RCC_CR_PLLON; 

 /* Wait till PLL is ready */ 

 while((RCC->CR & RCC_CR_PLLRDY) != RCC_CR_PLLRDY){} 

 RCC->CFGR &=~ (RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_SW);

 /*RCC_SetAHBPrescaler HCLK = SYSCLK / 1*/

 /*RCC_SetAPB1Prescaler PCLK2 = HCLK / 4*/

 /*RCC_SetAPB2Prescaler PCLK2 = HCLK / 2*/

 /*RCC_SetSysClkSource*/

 RCC->CFGR |= (RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_SW_PLL);

 /* Wait till System clock is ready */

 while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} 

}