Posted on February 19, 2016 at 06:44Hi all,
I am writing a program for the STM32F030 in which I want to update TIM3->CCR2 using a DMA transfer. This transfer will be triggered to control PWM waveform generation, although I have simplified the code below. Unfortunately I have run into some odd behavior that I cannot figure out. Consider the following code:
uint16_t c[3];
TIM_OCInitTypeDef TIM_OCInitStructure;
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
TIM_OCStructInit(&TIM_OCInitStructure);
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_Pulse = 432;
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
TIM_OC2Init(TIM3, &TIM_OCInitStructure);
c[0] = 0xff11;
c[1] = 0x1234;
c[2] = 0x4321;
DMA_InitTypeDef DMA_InitStructure;
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
DMA_DeInit(DMA1_Channel5);
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&TIM3->CCR2);
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)c;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_BufferSize = 1;
DMA_InitStructure.DMA_PeripheralInc = DMA_MemoryInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure.DMA_M2M = DMA_M2M_Enable;
DMA_Init(DMA1_Channel5, &DMA_InitStructure);
DMA_Cmd(DMA1_Channel5, ENABLE);
Once the DMA transfer has run, one would expect TIM3->CCR2 to contain the value 0xff11. This is not what appeared to be happening so I opened the memory browser in debug mode and found the actual register value to be 0x0011 after the DMA had run. So for some reason the DMA transfer is only moving the bottom byte rather than the half word specified, or there is some sort of problem writing to this memory location. The same issue applies for CCR1, CCR3, etc.
Does anyone have an insight into why this might be happening???
