No bits in RCC_CSR at power-on

[gds23]

Posted on May 11, 2010 at 19:43

No bits in RCC_CSR at power-on

[gds23]

Posted on May 17, 2011 at 13:50

If I poll the RCC_CSR reg at least 3 times I then see the ''reset reason'' bits appear after an unclean reset. Contracted ST app engineers. So far they have not confirmed or denied but, for now, this wfm:

main() { for (int i=0; i<10; i++)     if (RCC->CSR & 0xFF000000)          break; : :

[Ric Ricardo]

Posted on June 05, 2018 at 13:39

I have a similar problem with the RCC->CSR register, especially with the IWDG Reset Status bit.

Time Content of RCC->CSR

After power on and enabling IWDG 0x14000003

Then maybe after a second or less 0x34000003

If the status bits receive a clear right upon reading them for the first time with

RCC->CSR |= RCC_CSR_MASK_RMVF;�?

then the content of the RCC->CSR is 0x20000

Is the information of the reset cause of IWDG lazy loaded into the CSR register?

Have I missed a note somewhere that says something about the timing of this status bit?