Macro about Peripheral clock

[julienterrier39]

Posted on September 11, 2015 at 18:39

Hello,

someone would be able to explain mewhat's happen in the last two lines of this macro:

/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
* @brief Enable or disable the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before 
* using it. 
* @{
*/
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
UNUSED(tmpreg); \
} while(0)

-tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);

#define READ_BIT(REG, BIT) ((REG) & (BIT))

-UNUSED(tmpreg);

#define UNUSED(x) ((void)(x))

I understood everything except these two lines. Nb: No need to explain how works the bitwise & I can. I want only know why to have add these lines Thank you.

[Tesla DeLorean]

Posted on September 12, 2015 at 03:43

There's a couple of things going on here. The UNUSED macro uses the variable in a manner that does nothing, and stops the compiler warning that it's assigned a value and subsequently not used. The read back masking is a slight of hand causing the register to be read, the read has to happen, and forces the write buffer to commit the value to the RCC register first (the write gets differed through this buffering scheme, as it accelerates execution in the pipeline). This also avoids a hazard where someone enables the peripheral and then immediately starts programming registers in it, it allows the enable bit to get latched, and several cycles to occur prior to use. There mention of the issue in the errata.

[julienterrier39]

Posted on September 13, 2015 at 11:28

Thank,

I also found this explanation in the UM1725 but less technical compared to your explanation.

RCC Limitations
A delay between an RCC peripheral clock enable and the effective peripheral enabling
should be taken into account in order to manage the peripheral read/write from/to registers.
 This delay depends on the peripheral mapping.
 If peripheral is mapped on AHB: the delay is 2 AHB clock cycle after the clock enable
bit is set on the hardware register
 If peripheral is mapped on APB: the delay is 2 APB clock cycle after the clock enable
bit is set on the hardware register
Implemented Workaround:
 For AHB & APB peripherals, a dummy read to the peripheral register has been
inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.

Please clive1 what do you call ''ERRATA'' and where do you find it, could you give me the name of this document ? Merci beaucoup!

[Tesla DeLorean]

Posted on September 13, 2015 at 16:46

Googling STM32 and Errata, and they are off the Product pages via ''Design Resources''

http://www.st.com/web/en/resource/technical/document/errata_sheet/DM00037591.pdf

[julienterrier39]

Posted on September 13, 2015 at 21:31

2.1.13 Delay after an RCC peripheral clock enabling
Description
A delay between an RCC peripheral clock enable and the effective peripheral enabling
should be taken into account in order to manage the peripheral read/write to registers.
This delay depends on the peripheral’s mapping:
• If the peripheral is mapped on AHB: the delay should be equal to 2 AHB cycles.
• If the peripheral is mapped on APB: the delay should be equal to 1 + (AHB/APB
prescaler) cycles.
Workarounds
1. Use the DSB instruction to stall the Cortex-M4 CPU pipeline until the instruction is
completed.
2. Insert “n�? NOPs between the RCC enable bit write and the peripheral register writes
(n = 2 for AHB peripherals, n = 1 + AHB/APB prescaler in case of APB peripherals).

Data Synchronization Barrier.
Syntax
DSB{cond}
where:
cond Is an optional condition code, see Conditional execution on page 3-
Operation
DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB,
in program order, do not execute until the DSB instruction completes. The DSB instruction
completes when all explicit memory accesses before it complete.
Condition flags
This instruction does not change the flags.
Examples
DSB ; Data Synchronisation Barrier

Merci.