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Lukasz Przenioslo
Lukasz Przenioslo
Associate III
February 16, 2016
Question

JTAG without NJTRST

  • February 16, 2016
  • 6 replies
  • 5189 views
Posted on February 16, 2016 at 08:16

Hello there,

I have a general question regarding the NJTRST signal in a JTAG protocol. In STM32 datasheets, I read that JTAG can operate with only 4 pins, without NJTRST. I only assume it then uses regular #RESET pin to acomplish the goal? Please correct me if I am wrong. Also in the specification, what is confusing for me, it doesnt say anywhere that the regular #RESET pin is needed at any point:

https://www.dropbox.com/s/j7ygboalkyuo6zs/Zrzut%20ekranu%202016-02-16%2008.14.08.png?dl=0

I would really apreciate if one could explain me briefly the difference between NJTRST and #RESET, how they are needed otr not for JTAG. I know that NJTRST is some kind of inner reset for JTAG logic.
This topic has been closed for replies.

6 replies

re.wolff9
re.wolff9
Senior
February 16, 2016
Posted on February 16, 2016 at 10:16

I have not used jtag with STM chips... 

The more modern approach is to use ''SWD''. This is a two wire protocol, even though SWD stands for single wire debug. 

For SWD you need GND, SWCLK, SWDIO. The connectors on the ''discovery'' boards also have VCC, and reset. And a sixth signal that I don't remember / don't connect on my boards. I've found that the hardware reset from the debugger is sometimes necessary to make the chip behave as specified in the manual. Might be a software issue with my debugging software, but issuing the hardware reset has made the chip behave reliable. 

Is there a good reason you're inquiring about JTAG?

Lukasz Przenioslo
Lukasz PrzeniosloAuthor
Associate III
February 16, 2016
Posted on February 16, 2016 at 10:22

I am just wondering about the need of the TNJRST pin. Also I use JTAG whenever I can (whenever I have enough pins) because I think it is more reliable and faster than SWD. Maybe I am wrong.

stm32forum
stm32forum
Associate III
February 16, 2016
Posted on February 16, 2016 at 10:35

The more modern approach is to use ''SWD''. This is a two wire protocol, even though SWD stands for single wire debug. 

It's a one wire protocol, the second wire is used for the clock. All the data goes trough one wire, both direction.

TDK
TDK
February 16, 2016
Posted on February 16, 2016 at 19:11

For SWD, you need to connect the NRST pin if you want to debug through OpenOCD/ST-Link.  If you just want to program it, you don't need this pin.

It may be the same for JTAG, but I haven't used it.

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Lukasz Przenioslo
Lukasz PrzeniosloAuthor
Associate III
February 16, 2016
Posted on February 16, 2016 at 19:25

Thats not true. NJTRST is not even a part of JTAG circuit:

https://www.dropbox.com/s/ji9rvuh4i4tuz0t/Zrzut%20ekranu%202016-02-16%2019.26.11.png?dl=0
ilmars
ilmars
Visitor II
February 17, 2016
Posted on February 17, 2016 at 22:25

The TRST pin is an optional active-low reset to the test logic - usually asynchronous, but sometimes synchronous, depending on the chip. If the pin is not available, the test logic can be reset by switching to the reset state synchronously, using TCK and TMS. Note that resetting test logic doesn't necessarily imply resetting anything else.

It also means that either you don't use JTAG reset line function at all or use TRST, never generic RESET (which will reset whole chip and confuse debugger, your debug session and you including). 

Source: 

https://en.wikipedia.org/wiki/Joint_Test_Action_Group

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