Posted on March 09, 2015 at 18:43 Unfortunately yes, it's proprietary otherwise I'd show some excerpts. Quite a bit of work went into the driver, and the competition uses similar Cortex M controllers, so it isn't going to be available.
But knowing it can be done is half the design effort. I use TIM 9 for the RX DMA timer since it has a reset pin input, but any timer with a reset capable pin input works (not all timers support this). Overall my logic is to enable IRQ for the first character in a message, set up but not enable DMA for the rest of the message (largest possible size, 520 in my case), set up timer but not start it, and then wait for the first byte.
Soon as the first character arrives I stuff it in the buffer, turn off RXNE IRQ, enable the timer (30 bit times fits my inter-message gap for any data rate) and enable the RX DMA to complete the transfer.
If the timer overflows then it has found an inter-message gap. I stop the timer and RX DMA, which in turn triggers a DMA TC. The DMA TC signals a completed packet. Packet length is determined by remaining transfer count in the DMA register (max - remaining count). That's it, except for any line turnaround or starting a receive for the next message.
TX DMA is simpler. Set up the DMA for the message address and byte count, enable DMA, wait for DMA TC. At DMA TC the message is sent but the last byte may still be in transit, so I enable the USART TC interrupt. At the USART TC the last byte is complete and the line can turn from TX to RX mode.
I use FreeRTOS mutex flags to serialize access to the USART and DMA hardware, and a message queue with the packet address and length to pass the completed data on to the network listener. I don't pass the entire message because I don't want to move large amounts of data around in memory. Better to use a pool of message buffers than copy buffers.
