Is ADC sampling clock equal to system clock ?

[mehmet.karakaya]

Posted on December 30, 2016 at 13:40

hello dear forum,

I am trying to take 500 samples from STM32F103RC ADC with DMA

I wanna know if the ADC sampling clock equal to ADC clock or 

system clock 

for example ;

If I choose ADC clock = P2clock / 8 = 9 MHz 

and I choose sampling time 239.5 clock 

does this mean that 500 samples last ( 239 * 500 ) / 9000000 = 13 milisecond ?

thank you

#stm32f103-adc-clock

[Tesla DeLorean]

Posted on December 30, 2016 at 14:48

There is also the conversion time, which is dependent on the number of bits. The computation is in the reference manual as I recall.

For a specific 'sample rate', in the I want 1 KSps sense, you'd do better configuring a TIM based trigger rather than play games with the sample+conversion numbers and the limited subset of choices that provides.

[mehmet.karakaya]

Posted on December 30, 2016 at 17:39

hello thank you Clive ,

I have the following problem;

I want measure the peaks in the signal below picture

this is current signal from current transformer output of a power electronics device 

the signal is line synchronized as you expect ( but I already have PCB printed and I havenot made an HW interrupt for line zero crossing so I cant synchronize my ADC with the signal )

one idea which came into my mind 

is measuring more than 10 milisecond and finding the peak ( or 10 samples from both sides of peak and averaging the result ) with software 

my first question ; if I select ADC clock 9 MHz and sampling time 240 clocks and taking 500 samples with DMA - do the 500 samples last about 13 milisecond ?

second ; what other suggestion do you make to me ? how can I measure peak current from above signal picture with only having ADC input in my hand?

[Tesla DeLorean]

Posted on December 30, 2016 at 18:11

The conversion is an additional 12.5 cycles, so 239.5 + 12.5 = 252 cycles

500 samples with a 9 MHz ADC clock would be 14 ms

You can benchmark/qualify these things yourself by toggling a pin in a 500 sample DMA TC interrupt, or timestamp with DWT_CYCCNT

You could shoot to have a 10ms sample buffer, or one split it two halves, that you could process at 100Hz. ie find the peak, should remain in roughly the same spot in the buffer. If you used a TIM trigger, you could advance or r.etard slightly the sample rate to keep it centred, or follow it

[Seb]

Posted on December 31, 2016 at 07:37

How about filling up a SRAM buffer of ADC sample by DMA in circular mode (no interrupt) and activate the analog watchdog to capture by interrupt the DMA sampling area for analysis of peak value etc... ?

[mehmet.karakaya]

Posted on January 05, 2017 at 14:15

hello Clive ,

please I have one more question

if I scan 2 different analog inputs each with 239 cycles sampling time ,

does the sampling times overlap ?

or , do every single channel wait 239 cycles sampling before ADC conversion ?

i.e. for 2 channels conversion 2 x 239 = 478 cycles sampling time in total ?

thank you