i2c running reliable with higher priority interrupts ?

[uwe2]

Posted on September 12, 2011 at 11:43

Hello,

I am finalising a product with a STM32L15x CPU. Now I am fine tuning operation, and I have found no way to make I2C run reliabel, if there is another interrupt with higher priority beside the I2C. 1.) Is there any specification out, which describes the I2C in more details than the RM0038 or the I2C application notes ? (especially any timing related information ???) 2.) Is there somebody out, who has an I2C running reliable WITH other higher priority interupts ? Any hints are welcome. Maybe someone from ST can give more detailed informations about the I2C limits ??? #stm32-i2c-interrupt

[emalund]

Posted on September 12, 2011 at 14:32

I do not know about the ''L'' series, but DO read the errata, for the non-L the I²C is quite messy and workarounds are suggested in the errata

Erik

[uwe2]

Posted on September 12, 2011 at 15:42

Hello Erik,

I think it would be a good idea, if somebody from ST could clarify, if the STM32L has the same I2C implementation than the F series. I expect NOT. Cause in the Errata sheet of the L15x the I2C errors are different than the erratas f.e of the F103. So I assume that also the implementation is different. Otherwise I would expect in the STM32L15x Errata sheet to read, that the SAME erros like on the F devices are valid for the L devices. From: malund.erikPosted: Monday, September 12, 2011 2:32 PMSubject: i2c running reliable with higher priority interrupts ?

I do not know about the ''L'' series, but DO read the errata, for the non-L the I²C is quite messy and workarounds are suggested in the errata

Erik