hello.
I am implementing I2C slave with STM32F103C8T.
I2C is operated by a external master.
It must support Rx and Tx from 1 to 16 bits as shown below.
Purpose: To implement the following functions.
- Operates as I2C slave
- Write 1Byte address > Repeated start > Read 1~16 Bytes
- Write 1~16 Bytes
- image : Communication 16 byte read (Success)
Write 1 byte address during read operation
=> repeated start
=> Read 16 byte operation
=> Stop
At this time, Repeated start is not recognized intermittently. (issue)
- image : Communication 16 byte read (Fail)
Write 1 byte address during read operation
=> repeated start
=> ???
=> ???
Parameter Setting
NVIC Setting
The actual code written is below.
- image : Overriding Function
It referred to the I2C_TwoBoards_RestartComIT example.
In order to determine whether to enter the function through i2c_test_cnt, the data size of HAL_I2C_Slave_Seq_Receive_IT and HAL_I2C_Slave_Seq_Transmit_IT was limited. (tailored to communication packets)
- image : ISR, I2C_EV, Slave mode branch
=> i2C_test_cnt[1] : HAL_I2C_AddrCallback, I2C_DIRECTION_TRANSMIT
=> i2C_test_cnt[2] : HAL_I2C_SlaveTxCpltCallback, 1Byte Transmit complete
=> i2C_test_cnt[0] : HAL_I2C_AddrCallback, I2C_DIRECTION_RECEIVE, Repeat Start
=> i2C_test_cnt[3] : HAL_I2C_SlaveTxCpltCallback, 16 Byte Receive complete
Header recognition (ADDR, Set) does not occur after repeated start.
- Packets when communication fails include an Ack.
- The ADDR bit of the SR1 register is not set.
- The TRA bit of the SR2 register is set. (Data bytes transmitted, OK)
- SCL is fixed to Low in packets when communication fails. (It will be restored by resetting I2C on the MCU.)
- SDA is fixed to Low in packets when communication fails. (It will be restored by resetting I2C on the MCU.)
- This issue occurs intermittently.
