How is STM32F303 differential ADC input centered?

aaron · ‎2014-01-03

Posted on January 03, 2014 at 22:45

I have been unable to determine from the datasheets or application notes what the real behavior of the ADC in the STM32F303 is when in differential mode. This leads to two questions:

1) Can V_neg be greater than V_pos (assuming both are within the legal 0-3.3V range)?

2) How many counts does the ADC report when V_pos = V_neg?

Suppose that I have a balanced differential input (so V_pos + V_neg = V_cm), where both inputs can range from 0.6-2.2V and V_cm is approximately constant at 1.4V. If (V_pos = V_neg) maps to zero counts, then this can only usefully measure when V_pos >= V_neg. If (V_pos = V_neg) maps to half scale, and V_neg can be larger than V_pos, then the full 3.2V swing of the difference can be measured.

LT has a nice summary of different kinds of differential ADCs:

http://cds.linear.com/docs/en/product-selector-card/2PB_sar_input_types.pdf

I am really hoping the STM32F303 has a ''fully differential'' (unipolar) ADC. I just can't determine that from the available documentation.

Does anyone have more information? I may just have to breadboard this and see what it does, but I'd like to see published specifications if they exist. Thanks.

(edited to correct an error and to generally tidy up)

raptorhal2 · ‎2014-01-04

Posted on January 04, 2014 at 16:13

See Section 12.5.1 of the reference manual on setting an offset to produce a signed value.

Cheers, Hal

aaron · ‎2014-01-05

Posted on January 05, 2014 at 16:13

Thank you Hal for pointing me to the register for setting an offset.

This left the larger question of whether V_neg > V_pos is legal and what the mapping is, so this morning I tested it on a breadboard.

I put three 4.7K resistors in series between 3.3V and GND on a STM32 F3 Discovery board. I used the connections on either side of the middle resistor to generate 1.1V and 2.2V so I could have balanced inputs around a common mode of 1.65V. I then wired these to PA1 and PA2 in different ways, where PA1 was V+ and PA2 was V-. Note that I am assuming VDD = VDDA = 3.3V.

I am happy to report that it appears to be fully differential as I hoped. Specifically, I measured the following:

V+ (volts)

V- (volts)

ADC counts

3.3

0

4095

2.2

1.1

~2780

1.1

2048

1.1

2.2

~1603

0

3.3

~151

This also seems to indicate that the ADC input is compressed, so while the single-ended range is 0-3.3V, the differential input range is 0-3.3V on both inputs for a total swing of 6.6V.

I noticed that the output is a little bit biased. For instance, when (V_pos - V_neg) = 3.3V the output is 4095 counts, but when (V_pos - V_neg) = -3.3V the output is 151 counts when it should be zero. The difference between the 2.2V vs. 1.1V cases is also not symmetric around 2048. This is shown below:

V+ (volts)

V- (volts)

ADC expected

ADC actual

2.2

1.1

2730

~2780

1.1

2.2

1365

~1603

That is, in the second case, there is an error of about 300 counts, where in the first it is within about 50.

I also got a different result for (V_pos = V_neg = 1.1V) than for (V_pos = V_neg = 0V). When I grounded both inputs, the result was ~1903, where it was perfectly mid-scale (2048) when they were both 1.1V. I suspect that there is some bound on the common mode, or some nonlinearity that pops up when it swings too far to one rail, but I don't see that documented anywhere.

Hopefully this will save someone some trouble in the future. If anyone at ST could fill in any of the blanks (or explain why there seems to be bias), I'd appreciate it. I believe that the Discovery board lets PA1 and PA2 float so I shouldn't have been fighting any pull-ups or pull-downs. I had disabled these within the chip as well.

(edited to clean up formatting a little after once again the forum interface ate my post and I had to copy/paste in a backup I'd made)

raptorhal2 · ‎2014-01-05

Posted on January 05, 2014 at 19:03

Using a resistive networks for ADC inputs can produce inaccuracies if the sampling time is too low. See Table 67 in data sheet Rev 7 for guidance.

Cheers, Hal

aaron · ‎2014-01-06

Posted on January 06, 2014 at 14:42

Good to know. I did have the ADC configured for the minimum sampling time. If I build up a system around this the input will likely be from a differential amplifier, so I'll see what happens then. Thanks.