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How ADC integral linearity error is calculated?

Mateusz Kaskow
Associate II

From STM32F373xx datasheet, SAR ADC characteristics, page 99/137, for Vdda = 3V, i can see that

  • ED - Differential linearity error is max +/-1 LSB
  • EL - Integral linearity error is max +/-1.5 LSB

But in SDADC characteristics, page 111/137, the difference between ED and EL is much bigger, for example for single ended mode, gain = 8 and Vrefsd+ = 3.3V

  • ED is max 3.3 LSB
  • EL is max 35 LSB, so here i think 6 bits (!) from 16 bits of SDADC can be affected by this error

Could you please explain me why EL in SAR ADC and SDADC are so different?

Does it mean that 16 bit SDADC is NOT better than standard 12 bit SAR ADC?