Hardware Error in M3 and M4?

[damh]

Posted on November 29, 2016 at 13:23

if i call the assembly instruction ''sub sp, sp, 0xF8'' alias ''BE B0'' (instruction code), the code is executed as a ''nop''. Checked with F103 and L471.

Does anyone know about that or can confirm this? Is the assembly ''sub sp, sp, 0xF8'' forbidden? ''sub sp, sp, 0xF4'' or ''sub sp, sp, 0xFC'' are working correctly! Is there a way to forbid the compiler to use this specific command?

[damh]

Posted on November 29, 2016 at 14:18

Seems to be a debugger fault (why ever?).

[STOne-32]

Posted on December 05, 2016 at 15:30

Dear damh,

Could you share your debugger screenshot ?    and see what is really executed by the core in the Cortex-M3/M4 registers .

cheers,

[aaron239955_stm1_st]

Posted on December 05, 2016 at 20:17

are you running in user mode rather than supervisor mode?  The SP register may be protected as a special register unless you are running with the right privileges.  The chip by default comes up in supervisor mode, but if anything in your startup code, or later, changes this you could be dealing with a violation of the rules of the chip during operation that would not show up in the assembler since the latter does not know the context in which you will run the code.