HardFault and working reverse GPIO Pins

[Zek_De]

Posted on September 14, 2017 at 15:12

Hi friends,

I've got problems with STM32F0 series also same F1 now my real problem is getting a HardFault ,when I try to work with Nrf24lWhen process arrive this line 'TM_NRF24L01_SetTxAddress(&hspi1, TxAddress);' getting HardFault ,I see it with debug.Also extra matter is HAL_GPIO_WritePin(...); working reverse ,why is it ? Everything seems good under the codes.I'm thinking about Hardfault related with stack maybe I dont know.I've sent project.I havent sloved it for a long time but now again I need it.Stm32f4 is Ok .No HardFault error.Same code ,same process with stm32f4 Note: this post was migrated and contained many threaded conversations, some content may be missing.

[Tesla DeLorean]

Posted on September 14, 2017 at 16:55

Use a debugger, and a half decent Hard Fault handler and look explicitly at the assembler instructions causing the fault, it's NOT complicated.

The CM0 is going to be intolerant of memory alignment issues, compared to CM3/4 processors.

If you think its the stack, then look at that, determine if it is big enough and how much you're using of it.

 

[Zek_De]

Posted on September 14, 2017 at 17:36

Thank you answer ,

First I didnt understand this sentence what I need to do ,and I send my project .rar file .I'm gonna look forum you sent me.Ä°f you control project ,I will be so glad.

[Tesla DeLorean]

Posted on September 14, 2017 at 18:02

I'm busy with my own work, I can't be digging into yours.

Stack size is in startup_stm32f030x6.s, you have 1024 bytes, is that adequate?

Look at the code that is faulting, what is it doing, it will give you a clear perspective of what the CPU dislikes. I don't have hardware to replicate, you'll need to own the detective work. The Cortex-M0 has a smaller instruction set and doesn't like misaligned data, ie 16 or 32-bit read/write to ODD addresses. Hard Faults will also occur if you stray outside defined memory regions with RAM or registers behind it.

[Zek_De]

Posted on September 14, 2017 at 18:27

TThank you again,

Some part in startup .Now How alterations I should go.By the way it is same with stm32f4 startup

Stack_Size EQU 0x400

AREA STACK, NOINIT, READWRITE, ALIGN=3

Stack_Mem SPACE Stack_Size__initial_sp; <h> Heap Configuration; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>; </h>

Heap_Size EQU 0x200

AREA HEAP, NOINIT, READWRITE, ALIGN=3

__heap_baseHeap_Mem SPACE Heap_Size__heap_limit

[Tesla DeLorean]

Posted on September 14, 2017 at 19:39

Like I said, I don't know if it is the stack, you'd need to evaluate that in your specific context.

Hard Faults are gross failures, the CPU will indicate exactly where things went wrong, and you should examine the code that causes the fault/failure to see what it didn't like.

For code that exhibits specifically CM0 vs CM4 failure the alignment issue would be a prime suspect. ie someone casting an 8-bit pointer into a 16-bit one for an odd address.

[Zek_De]

Posted on September 14, 2017 at 22:49

Hi again ,I did debugging and I went in HartFault function on this line 

hspi->Instance->DR = *((uint16_t *)pData);  a few codes in ' HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) 'while (hspi->TxXferCount > 0U) { /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ hspi->Instance->DR = *((uint16_t *)pData); pData += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { *((__IO uint8_t *)&hspi->Instance->DR) = (*pData++); hspi->TxXferCount--;

What are you thinking about what I can do?

[Zek_De]

Posted on September 14, 2017 at 22:54

in these codes 

TM_NRF24L01_SetMyAddress(&hspi1, MyAddress);

TM_NRF24L01_SetTxAddress(&hspi1, TxAddress);

SetMyAdress(...); is working, but 

SetTxAddress(...); is not working ,they contain about same codes like this following below.

void TM_NRF24L01_SetMyAddress(SPI_HandleTypeDef *hspi, uint8_t *adr) { NRF24L01_CE_LOW; TM_NRF24L01_WriteRegisterMulti(hspi, NRF24L01_REG_RX_ADDR_P1, adr, 5); NRF24L01_CE_HIGH;}

and

void TM_NRF24L01_SetTxAddress(SPI_HandleTypeDef *hspi, uint8_t *adr)

{ TM_NRF24L01_WriteRegisterMulti(hspi, NRF24L01_REG_RX_ADDR_P0, adr, 5); TM_NRF24L01_WriteRegisterMulti(hspi, NRF24L01_REG_TX_ADDR, adr, 5);}

and adresses are these

uint8_t MyAddress[] = {

0xE7, 0xE7, 0xE7, 0xE7, 0xE7};/* Receiver address */uint8_t TxAddress[] = { 0x7E, 0x7E, 0x7E, 0x7E, 0x7E};

[Zek_De]

Posted on September 14, 2017 at 23:07

and these are stm32f4 seriesa few codes related previous sending code in HAL_SPI_Transmit

/* Wait until TXE flag is set to send data */

if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { *((__IO uint8_t*)&hspi->Instance->DR) = (*pData); pData += sizeof(uint8_t); hspi->TxXferCount--; }

[Zek_De]

Posted on September 14, 2017 at 23:16

My mistake this writing is cancelled ,for Stm32f4 different part ,dont consider last one.