GPIO: What Happens at the MOSFET Level When You Run Your Code? - Part 1

[Abdusselam]

:warning:Note: The internal GPIO structure has been simplified for better conceptual understanding. (Components such as
ESD protection diodes, pull-up and pull-down resistors, etc., are not shown.)

:warning:Warning / Disclaimer This analysis is based on my personal study and interpretation of technical documents. Therefore, I cannot guarantee that it fully represents the actual internal behavior of all STM32 microcontrollers. This is a simplified conceptual model for educational purposes.

INTRODUCTION

In this document, we will examine how our code affects GPIO units at the MOSFET level. Our analysis focuses on the MOSFET switching logic in General Purpose Output (Push-Pull, Open-Drain) and Input Mode (Analog and Alternate Function modes are not included in this analysis). I used the following documents as references for this analysis and the visuals:

• AN4899 Application Note (STMicroelectronics)
• RM0365 Reference Manual (STM32F3 series)

Since this analysis is based on the STM32 architecture, we will focus on MODER, OTYPER, and ODR registers.

I would be very happy if ST employees or experienced engineers could check my work. Please let me know if you find any mistakes or if there is anything I can improve. I am eager to learn from your feedback!

How to read the table?

1. Register Selection: Select MODER, OTYPER, and ODR values in order.

2. Output Control: The Output Controller sends the resulting Signal 1 and Signal 2 to the MOSFET Gates.

3. Note: "X" indicates that the selection is not available or has no effect for that mode.

PIN MODES

1. OUTPUT MODE

1.1 What is Push-pull?

Briefly, it is a MOSFET pair that forces the line to a specific logic level. It is easier to understand with an example:

• To make the line HIGH: PMOS is ON (conducting), NMOS is OFF (cut-off).
• To make the line LOW: NMOS is ON (conducting), PMOS is OFF (cut-off).

1.2 What is Open-drain? 

Briefly, the PMOS is always OFF (cut-off). Only the NMOS switches between ON and OFF states. This is why we use this mode for I2C. As you may remember, in I2C, the line is either released (floats/HIGH with pull-up) or pulled LOW.

2. INPUT MODE

In input mode, both MOSFETs (PMOS and NMOS) are in the OFF (cut-off) state. This allows the external signal to be read correctly by the processor (via the Input Data Register).

QUICK NOTES ON REGISTER STRUCTURES

1. The two most fundamental modes of a GPIO are Input and Output. We use the MODER register to select between these modes.
2. If Input Mode is selected: This step does not apply. If General Purpose Output Mode is selected: We use the OTYPER (Output Type Register) to choose between:
   1. Push-pull
   2. Open-drain
3. ODR (Output Data Register) register stores the output data. Example: When the pin is in Push-pull mode, if the relevant bit of the pin in the ODR structure is 1, a HIGH signal is generated; if it is 0, a LOW signal is generated.

 

[unsigned_char_array]

I don't understand the purpose of this post. It's not a question, but doesn't seem to provide much information either. And why does this post have the labels GPIO-EXTI and STM32F3 Series?

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@Abdusselam wrote:

:warning:Note: The internal GPIO structure has been simplified for better conceptual understanding. (Components such as
ESD protection diodes, pull-up and pull-down resistors, etc., are not shown.) 

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The devil is in the details. I wouldn't leave anything out. Certainly if you want to show what happens on the lowest level.

The basis for all GPIOs of MCUs is very similar. You have a high side switch and a low side switch that can be (somewhat) independently controlled and some input circuit. That's basically it. But it's the details that differ. What are the peculiarities and pitfalls?

Things to consider:

• Different drive strength modes. Important for crystals. Too low and it won't work reliably, too high and current consumption is higher.
• Different speed modes. Slow for slower transients for EMC? Or also lower power consumption?
• Weak pullup and weak pull down. What is their U/I-curve? What is their tolerance? On during reset?
• schmitt trigger input or basic input with illegal zone?
• true open drain or simulated open drain?
• 5V tolerant or not?
• always check errata sheets!
• check known issues on this website: http://www.efton.sk/STM32/gotcha/index.html

Another idea: since ST doesn't document the exact low level silicon implementation of their GPIO peripherals. One idea is to take an x-ray of the peripheral area.

[Abdusselam]

You are right. I am a Mechanical Engineering student who is passionate about learning embedded systems. I thought sharing my simplified charts as 'Part 1' could help other beginners during their learning process, with the plan to make them more complex as I learn. 

However, based on your feedback, I realize that sharing a complete and detailed system after finishing the whole process will be much more beneficial. I will pause my posts for now and focus on gathering deeper information from the resources you suggested. Thank you for the guidance.