FSMC SRAM unused pins clarification

[mmueller]

Posted on September 15, 2011 at 16:39

The STMicro FAQ states that when you configure FSMC for SRAM that the unused pins can be used for general purpose I/O.  Does that mean you cannot use the any of other alternate functions of those pins if you are using the FSMC?

#fsmc-sram

[aqueisser]

Posted on September 15, 2011 at 17:55

Should be ok to use them for any other purpose. We're using the upper address lines for 4bit trace and it's not a problem.

Andrew

[Tesla DeLorean]

Posted on September 15, 2011 at 18:01

The STMicro FAQ states that when you configure FSMC for SRAM that the unused pins can be used for general purpose I/O.  Does that mean you cannot use the any of other alternate functions of those pins if you are using the FSMC?

The evidence I've seen suggests that they will conflict with AF usage, for instance one of the eval boards uses an I2C device attached to an unused NADV pin, for the I2C to be functional the clock to the FSMC is turned off. I could see this being very messy if something tries to access external memory under interrupt. One of the documentation problems I have, is the lack of a good diagram of how the pin function muxing actually works. I suspect there are some AND/OR constructs.

[Tesla DeLorean]

Posted on September 15, 2011 at 18:10

Should be ok to use them for any other purpose. We're using the upper address lines for 4bit trace and it's not a problem.

I suspect it's going to be very dependent on the nature of the AF signals in question, and whether they lend themselves to time divided multiplexing. This could be problematic for something being used as a clock output, unless gated by a chip select/enable. Getting random glitches would not be good. As a data output latched on some other edge, probably less so. I think one of the areas to consider is whether the operation of the FSMC for an external memory access, or DMA, may tread on normal operation of the other peripheral, and interrupts, and disparity in bandwidths. ie some burst of asynchronous activity in the midst of the other peripherals signalling.