FSMC multiplexed mode
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‎2009-11-07 8:56 AM
Posted on November 07, 2009 at 17:56
FSMC multiplexed mode
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‎2011-05-17 4:29 AM
Posted on May 17, 2011 at 13:29
I would like to use the FSMC in multiplexed mode. Which 16 lines are used as the multiplexed bus AD[15:0]?
A[15:0] or D[15:0] ? Also, I plan on using a SRAM (in multiplexed mode, 16 bit data access). Of course there will be an external address latch. Nowhere in the datasheets or reference manuals is a timing diagram for SRAM in multiplexd mode shown. However, it looks like the NOR memory timing will work for this. Since I'm using 16 bit data access, do I need to be concerned with ''byte lane'' signals ? Thanks-Options
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‎2011-05-17 4:29 AM
Posted on May 17, 2011 at 13:29
Found the answer on multiplexed lines.
Bit 1 MUXEN: Address/data multiplexing enable bit. When this bit is set, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories: 0: Address/Data nonmultiplexed 1: Address/Data multiplexed on databus (default after reset) Still need success stories of multiplexed, 16 bit SRAM access.