External SRAM interface problem

[zeros_and_ones1991]

Posted on February 15, 2014 at 11:46

I got IS62WV12816BLL 128K * 16 bit SRAM to interface with STM32F207ZG , the problem is that i can not write properly to the SRAM , when i write say a word , i find that many addresses are written and only half the word is written correctly ...... i also see the value of the SRAM content changing as im moving to other breakpoints in the debug session ...... any suggestions ?

[Tesla DeLorean]

Posted on February 15, 2014 at 15:02

That would suggest it's not interfaced, or configured, properly.

I'd start by verifying the physical connectivity, and ideally have an EVAL board with a similar chip/configuration to test and understand the configuration and usage. Your post lacks any supporting schematic and configuration code.

[zeros_and_ones1991]

Posted on February 15, 2014 at 19:25

Thx for Replay Clive ...... Here is the schematic of both boards (SRAM and STM32) .........

and i used the SRAM code built-in ''system_stm32f2xx'' .......... and here is the configuration as i modified it FSMC_Bank1->BTCR[2] = (0x00000011)|(1<<12); FSMC_Bank1->BTCR[3] = 0x00010422; FSMC_Bank1E->BWTR[2] = 0x0fffffff; the thing is that on the SRAM board , they always have 26 address lines , while the SRAM chip has only 18 , but i knew i can use only the actual address lines ........ any help? ________________ Attachments : IS62WV12816BLL_SRAM_Board_SCH.pdf : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I1FJ&d=%2Fa%2F0X0000000bkG%2FLwMvSzKTzR9Y5hxnYn9T5xTIpWaoJP78QX8qpxv2Cgc&asPdf=false

[zeros_and_ones1991]

Posted on February 15, 2014 at 19:28

The Schematics

________________ Attachments : schamtics.rar : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I1Bx&d=%2Fa%2F0X0000000bkE%2FYh3VjlAuBOnYcJr1Qia4berLQ.VbQk.oCjpLaVxJYqk&asPdf=false

[Tesla DeLorean]

Posted on February 15, 2014 at 20:14

Ok, and how to the 28 pin headers on the SRAM board relate to the 36 pin headers on the PORT207?

The correct connectivity is critical here, along with all the pin initialization on the processor side. With the address bits you will simply see the SRAM repeated through the upper address range. ie you'll see shadows / ghosts of the same content at different multiples of the SRAM physical size.

[zeros_and_ones1991]

Posted on February 15, 2014 at 21:06

I'm using wires to connect the IOs ........ That is really starting to be frustrating.

[Tesla DeLorean]

Posted on February 16, 2014 at 02:10

Yeah, ~56 wires, hopefully not too long. You'd need to enumerate them if you want them cross-checked.

http://www.keil.com/forum/24850/

[zeros_and_ones1991]

Posted on February 16, 2014 at 03:37

Well , I would not worry about cross-talk ...... because im operating on the internal 16 MHz for now , so its kinda slow , plus the wires are 20 cm long . ......... really confusing.

[Tesla DeLorean]

Posted on February 16, 2014 at 16:04

!cross-talk

''He's making a list, And checking it twice''