Dynamic System Clock Frequency

[keepcoding]

Posted on October 29, 2013 at 12:51

Hi

I wonder if there are any negative side effects when changing the system clock speed dynamically. I have an I2S audio samples transfer running (via DMA) and therefore, the CPU is put into sleep mode and the DMA interrupt wakes it up periodically. During this sleep period, the system clock is set to 8 MHz. When the CPU wakes up, the clock speed is set back to 64 MHz. Is this a bad idea? How does DMA / I2S cope with changing system clock speed?Btw, it's a STM32F3 Discovery board.Any advice is appreciated.

[Tesla DeLorean]

Posted on October 29, 2013 at 13:15

The dividers will keep fixed ratios, your problem would be the state of the internal count at the time of the frequency change. You'll get some odd output until it resyncs (ie phase noise, frequency modulation)

[keepcoding]

Posted on October 29, 2013 at 13:24

ok... so what would you suggest then? Using a fixed frequency?

Or will this 'phase noise, frequency modulation' be low enough to be neglegible? I don't need high quality audio, it's just an 8 kHz stream from a microphone.

[keepcoding]

Posted on October 29, 2013 at 13:24

sorry, double post

[Tesla DeLorean]

Posted on October 29, 2013 at 16:35

I don't know, you'll have to evaluate.

It is possible to change the ratios of multiple clocks to maintain nominally the same output frequency. ie APB clock, and USART baud divider. Unfortunately you're not likely to be change the all simultaneously. Depending on the clocks and their frequencies, what you're likely to observe is several cycles neither at the original periodicity, nor the the new periodicity, as the transition is completed. You'll need to examine the consequences, and whether it would make sense to disable/blank clocks/peripherals during the transition.

[keepcoding]

Posted on October 30, 2013 at 08:37

Thanks a lot for your advice.

I have one more question though: At which frequency does DMA run and what's the lowest frequency for DMA and I2S such that it still works? I couldn't find anything useful in the reference manual about this...

[keepcoding]

Posted on October 30, 2013 at 14:42

I'm having problems to understand what happens with the I2S which has its own clock generator... because there is no prescalar for the I2S clock, the speed will vary from 8 to 64 MHz. How does the I2S clock generator manage to keep a constant rate with a changing system clock?

From the ref. manual: ''The I2S uses its own clock generator to produce the communication clock when it is set inmaster mode.''So does this mean the I2SxCLK isn't needed at all if the I2S is configured in slave mode? So a change in the system clock frequency won't affect it?

[Tesla DeLorean]

Posted on October 30, 2013 at 15:14

The clock tree suggests the I2S gets it's clock prior to the AHB/APB dividers, or externally.

I'm not clear what you are changing. The I2S peripheral needs to be clocked, and this is perhaps a separate issue from the fact that a slave is going to expect a data clock input.

[keepcoding]

Posted on October 30, 2013 at 17:38

''

The I2S peripheral needs to be clocked''

So it needs to have a clock (either external or system clock) even in slave mode? I am changing the frequency of the ''system clock'' (from 8 MHz in sleep to 64 MHz in run mode) and therefore also the clock for the I2S peripheral. The I2S block diagram in the reference manual (p739) says that it has its own clock generator. So my question is: does it hurt when the input to the clock generator isn't constant (i.e. 64 MHz)?

[Tesla DeLorean]

Posted on October 30, 2013 at 18:26

The I2S is part of the SPI peripheral, in SPI mode it uses the APB bus clock to generate a shifting clock. In I2S mode this base clock can come from the sources in the clock tree (I2SxCLK from I2S_CKIN or SYSCLK), and then divided down by the ''I2S clock generator'' which has a more complex divide down circuit (8-bit + 1/2 a bit ODD/EVEN) compared to the 3-bit for the SPI interface.

Unless I've got my master/slave functions mixed up the generation of the clock is a MASTER issue, the SLAVE derives clocking from a master. The provision of an external clock source for a master (I2S_CKIN), is that the STM32 is awful at clock generation at desirable frequencies. All the dividers are integer, and based on decimal crystals (ie 12.000 MHz), and not audio magic crystals (ie 12.288 MHz, 11.2896 MHz) For a stable clock on an audio master, I'd probably look to push HSE out of MCO, and pulling than back in I2S_CKIN. Or use an external oscillator at a magic frequency, and use HSE_IN + I2S_CKIN, this however would preclude USB operation.