Hello,
We have a STM32H755 with an FRam (similar to SRAM) module attached to the FMC. We have been seeing CPU exceptions when the M4 core tries to access (read only) the same memory location the M7 core is writing to.
So, it seems that the FMC does not arbitrate between the two cores... Is that correct? or do we potentially have the FMC configured incorrectly.
We have the FRam memory address region configured in the MPU as shareable (M7 - read/write) and read-only (M4 - reads only) and tried with cache disabled as well with same cpu exception...
Thanks,
-mike
