Does the stm32f417 have cache capability? Is it disabled by default?

[santosh239955]

Posted on January 20, 2015 at 15:40

According to the datasheet it says, cache is turned off and art accelerator is on. 

http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00035129.pdfSo by default the cache is turned off unless the mpu is programmed according to the memory regions given in the datasheet.Since, if cache is present and used, it might take less number of cycles to complete a certain set  of instructions in function which are repeating. #eeprom #stm32f4-cache #tags-are-pointless #rewrite #stm32f417 #stm32f #flash #!twitter

[Tesla DeLorean]

Posted on January 20, 2015 at 17:07

Well it's not a processor cache, but does sit in front of the flash array, and handles the large width of the flash lines, and the wait states.

As the processor starts at 16 MHz there are no wait states on the flash, when you switch to 168 MHz you're going to need 5 wait states to get down to the speed of the flash (say 35-42 ns). The ART caches most frequently used lines, on a cache hit it delivers the instructions to the prefetch unit faster than RAM. On a miss you take the ~5 cycle hit to fetch the whole flash line, and then subsequent words within that line are free. So both code that repeats, and code that doesn't branch, will be net winners. So yes, by default it's disabled, but the processor is also running very slowly.

[santosh239955]

Posted on January 20, 2015 at 18:22

Thanks clive. So, its not actually a cache which comes with ARM core. But, it is by STM. The main purpose being to serve small size cache.

[Tesla DeLorean]

Posted on January 20, 2015 at 20:20

The Cortex-M[0,3,4] do not architecturally have a cache, the ART is added by ST, it's of a reasonable size, but only helps with FLASH, not slower external memory (SRAM, SDRAM, NOR, etc)