2020-10-30 05:57 AM
Are there anyone to know that gpio pin quantity to maximum current limit relation?
2020-10-30 06:10 AM
The datasheet certainly doesn't think so. Why would it change based on the number of pins?
2020-10-30 06:12 AM
Why, wouldn't it have more to do with the distribution of power, and the trace widths in the metal layers?
The parts share a common die, the bond out and lead frames might help localized current distribution/paths.
2020-10-30 07:03 AM
Because, more pin ,more vdd quantity i thought that more vdd more total gpio pin current out
2020-10-30 07:06 AM
for example at 100 pin 5 vdd, 144 pin 10 vdd existed , i thought that more vdd more bound out and more total gpio current
