Confusion on STM32F407 DMA FIFO mode, Please help

[sunnyqd]

Posted on May 04, 2015 at 06:42

Hello everyone,

Nowadays, I'm trying to figure out how the FIFO of DMA works. But get stumbled with the DMA memory to peripheral mode with FIFO enabled.

Firstly, the STM32F4 ''RM0090 Reference manual'' P.219 ''Memory-to-peripheral mode'' which describes:

When this mode is enabled (by setting the EN bit in the DMA_SxCR  register), the stream immediately initiates transfers from the source to

entirely

fill the FIFO. Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination. When the level of the FIFO is

lower than or equal to

the predefined threshold level, the FIFO is

fully reloaded

with data from the memory.

Note the word ''entirely'' and the ''fully reloaded'', shouldn't it be the ''FIFO threshold''? If so, it also conflicts with ''lower than or equal to''. I'm confused about these two sentence.

Moreover, in the same mode, it says ''

When this mode is enabled

,

the stream immediately initiates transfers

''. Assuming I have a buffer u16 M[8] defined in memory, and set the FIFO threshold level to 1/2 (4 half words), the peripheral burst 4 beats of u16. The NDTR is 8.

So, when the DMA stream is enabled, the M[0]~M[3]

immediately

fill the 1/2 FIFO. And when the DMA trigger arrives, the 1/2 FIFO data sends to the Peripheral, also

at the same time (?)

the FIFO re-fills the 1/2 with M[4]~M[7].

If this is how it works. Assuming, after the DMA stream is enabled, and lately I changes the data of M[0]~M[3], and the DMA trigger arrives. The data in the 1/2 FIFO is the pre-M[0]~pre-M[3] value, rather than the M[0]~M[3] I just changed?

If so, there is a delay between the value I write into M[0]~M[3] and the value the Peripheral receives, due to the FIFO structure.

If my assumption above is correct, is there some way to flush (meaning

delete

)the preloaded value in the FIFO? As a consequence, I could do the following procedure: modify M[0]~M[3], flush (delete, not to peripheral) 1/2 FIFO, re-fill 1/2 FIFO with M[0]~M[3], waiting for DMA trigger.

Please help me out!

[sunnyqd]

Posted on May 06, 2015 at 15:50

gonzalez,

Yeah, things will become uncertain if DMA is used in this circumstance. Your advice is helpful. I will reconsider this architecture and try to figure out another way :> thanks again