Clock generation from 14.7456MHz

[andreas239955_st]

Posted on March 26, 2014 at 11:26

In the user manual: AN2606 - STM32 microcontroller system memory boot mode it describes that when using a 14.7456MHz clock crystal the bootloader configures the PLL to run at 48MHz. How is this achieved? What settings do I need to get this clock frequency?

Best regards,Andreas

[Tesla DeLorean]

Posted on March 27, 2014 at 04:34

Figure it benches HSE vs HSI, and then generates ~48 MHz with perhaps 0.16% error.

[andreas239955_st]

Posted on March 28, 2014 at 10:06

Oh, I guess that could be done. I tried running the USB PHY at 5*14,7456*2/3=49,152MHz and it still worked, but I wouldn't be happy to deliver a product with this.

So I guess the best approach would be to calibrate the HSI using the HSE and then run the USB of that one? :\Best regards,Andreas

[Tesla DeLorean]

Posted on March 28, 2014 at 16:34

((14.7456 / 15) * 195) / 4 = 47.9232 MHz

(1 - (47.9232 / 48.0000)) * 100 = (1 - 0.9984) * 100 = 0.16 %

[Tesla DeLorean]

Posted on March 28, 2014 at 16:37

Could have sworn the post originally referred to an STM32F4 part, although I may have inferred it from the app note.

49.152 has a 2.4% error Further more, you should know what crystal you're using, the boot loader doesn't know, which is why it has to make computations. I believe it could use a larger range of crystals than the app note suggests, as there are no specific references to 14.7456 MHz that I can see.

[Tesla DeLorean]

Posted on March 28, 2014 at 21:15

freq=7456
cpu= 9616, usb= 9232, err= 0.16%, pll_m=15, pll_n=195, pll_p=8, pll_q=4
cpu=9945, usb= 9984, err= 0.00%, pll_m=14, pll_n=319, pll_p=2, pll_q=7