Can the L4R5 OCTOSPI interface be configured as a slave

[JButl]

Hi,

Can the L4R5 OCTOSPI interface be configured as an SPI or Hyperbus slave so that it's flash memory can be accessed and addressed via SPI from a master device?

Is it possible to configure the L4R5 OCTOSPI so that the device appears as an external flash memory to an SPI master device?

[S.Ma]

I would think to put this in the STM32 2020 wish list...

[Tesla DeLorean]

The complexity of doing that seems to offer little in the way of rewards.

Perhaps you can make some dual-port mailbox memory with a CPLD/FPGA ?