The cache has lines that are 128-bit wide, this is 16-bytes, aligned on 16 byte boundaries, and likely matches the geometry of the FLASH, or two adjacent lines within the FLASH. The content from FLASH can be transferred directly to the cache line, and the words are then served to the prefetch of the processor. On a cache hit this occurs within the same cycle, compared to 1-cycle later from SRAM, etc.
There are 64 of these lines, which presumably will be flushed using an LRU manner.
