Baudrate for USART

[roderick1983]

Posted on December 28, 2009 at 20:34

Baudrate for USART

[tomas23]

Posted on May 17, 2011 at 13:35

Hello picguy, I'd argue, because the 16x bigger clock is used to position the sampling points within the bit period and for oversampling (see RM).

There is no more space for fractional prescaler here within those 16 clock cycles, so it must be implemented in the prescaler itself, eg. like a phase modulation divider?

[akaiser9]

Posted on May 17, 2011 at 13:35

Quote:

USART1 for 9600 baud I would load USART_BRG with 72000000/(16*9600) and let the assembler or compiler do the arithmetic. Besides the question of 36MHz bus clock vs 72MHz system clock, that's what you would do if it were not a fractional divider, but the usual x16 baud rate frequency divider. In fact, what you really have to do is to load BRG with busclock/baudrate. The x16 sampling frequency is compensated for by the 4 bit fractional part, so the integer part of BRG is your busclock/(16*baudrate). But the identity of fraction length and x16 sampling is nice but pure chance. Some other device has a 5 bit fractional part but still x16 sampling. Both the reference and the periph lib take different approaches, being quite a bit more complex that this simple calculation, but other than rounding differently they end up the same. [ This message was edited by: prx on 29-12-2009 01:19 ]