2013-10-02 02:24 AM
Hi all,
I probably made a mistake in my first layout for STM32F103RE (LQFP64), with SDIO bus. My 400 KHz SDIO_CLK output is not consistent on oscillo : I see variations in the levels of the HIGH and LOW that vary with a fixed period :- sometimes, HIGH+3.3 and LOW_0V are both correct,- then HIGH level decrease, and LOW increase- until HIGH and LOW levels are nearly the same at 1.6VThis variations are repeatable at a fixed period : approx 4 times the 400 KHz period.The oscillations in levels are awefull when using HSE (8 MHz) as source for PLL at 72 MHZ, and are still visible, and probably a problem too, when HSI is used as a source for PLL at 64 MHz.When using HSI, HSE is OFF : RCC_HSEConfig(RCC_HSE_OFF);I tried to cut the line of the GND return path of the Crystal too : same result...Problem is the same with a 400 KHz PWM with TIM5.Bad layout I'm afraid of. I was thinking about bad decoupling perhaps ?What I did for decoupling : 0.1uF CER on each VDD and VDDA, +4.7uF CER on VDD3 according to datasheet.VBAT is at 3.3V, but without decoupling capacitor.Do you see any error in my decoupling schem, anything I should work at ???Thanks in advance for your help ;) #sdio-decoupling-stm32f1032013-10-04 05:51 AM
My mistake,
After checking with a ''real true'' oscillo : levels are perfect. My little 1 MHz was not adapted to a 400 KHz reading...But I still have a problem concerning SDIO initialization (clock PLL 64 MHz on HSI) :In SD_PowerON() function:CMD0 : SD_OKCMD8: SD_OK, SDIO_STD_CAPACITY_SD_CARD_V2_0 detected Then ACMD41 loop : First CMD55 : SD_OK First CMD41 : SD_OK First SDIO_GetResponse(SDIO_RESP1) = 16744448 = 111111111000000000000000 -> validvoltage = 0s
econd CMD55 : SD_CMD_CRC_FAIL !!!I tried a lot of things, but it still always the same result.My SDIO is probably well connected, with appropriate pull-up 47K on each dataline, lines very short. VDD is 3.3V steady.I see good communication on CMD line, but a single pulse on D[3:0] only...Please help !!! ;)