The way you generate the 1.1kHz is by the time it takes to perform all the ADC required conversions, half of them with GPIO low, half of them with GPIO high.
Because the callback is within interrupt, jitter will come if other interrupts delays from time to time yours. (USB, etc...). The PWM frequency is not accurate and it will definitely stop if you put a breakpoint in the callback.
Usually, we try to rely on the HW so that SW is non critical for the signals generation with precise timings.
In this case, we would generate the PWM and check how many ADC samples filled the buffer. Half of them would be for high level, the other half for the low level (exluding the ones near the boundaries).
This way, if the SW stops, the PWM may continue. And if you adjust the ADC sampling time, the number of conversions will vary and you'll still be able to calculate an average.
Make sense? There would be still different scenarios to make it better, this is the way to look at the implementation.
