ADC noise STM32F103RB

john1389 · ‎2016-07-22

Posted on July 23, 2016 at 02:44

What configuration parameters (clock freq, sampling clock count, etc.) can I tune in order to minimize ADC reading noise when sensing a relatively low speed signal?

I am currently getting about 10 to 20 LSB difference in high to low reading, for constant DC input on Nucleo CubeMX Keil.

So far, I tried timer triggered DMA and polling modes. Will different modes affect noise performance?

How about sensing a large number of samples and calculate average? Is noise reduced by square root of sample number?

#adc-noise-tuning

raptorhal2 · ‎2016-07-24

Posted on July 24, 2016 at 23:24

In my experience, modes do not affect ADC conversion noise.

The list of application notes available for your device includes one on ADC conversion accuracy that is well worth reading. It describes how to determine the sampling clock count for accuracy.

Noise levels are reduced by oversampling and averaging as you stated.

Check the noise level on your signal to make sure you are working the right problem.

Cheers, Hal