ADC in dual interleaved mode in stm32f4 discovery

[hokus]

Posted on October 17, 2015 at 18:13

Hi, i have problem with determing number of cycles.

If i run ADC in dual interleaved mode with this parameters:  ADC_TwoSamplingDelay_5Cycles + ADC_SampleTime_3Cycles with resolution 12b on the first run of adc, data will be avaiable after 5 cycles, but on the second run after 10 cycles and so one ?

http://i60.tinypic.com/fcvevq.jpg

Did adc need to end of conversion with the same interval of cycles ? If yes then what are correct values for 12 bit resolution with sample time equals 3 cycles to execute with maximum speed. In library directory STM32F4xx_StdPeriph_Examples there is example but for 8 bit resolution and 6 cycles of delay.

[Tesla DeLorean]

Posted on October 17, 2015 at 19:10

The Reference Manual seems to infer it's every 17 cycles (3 + 12 + 2), and  3 + 2 = 5

The alternate interpretation is that you get samples from each at 15 cycles, slewed by 5 cycles. The way one can validate what's happening is to use DMA and time 100 or 1000 samples across the TC intervals. ie Toggle a GPIO in the TC Interrupt and scope it, or bench against a free running timer of know frequency. I'm not big into the ADC, but when I don't understand how something works, or the manual is awkwardly presented, I go an test and validate my model of how it should work, with how it actually performs. Hal might have some better insight.

[raptorhal2]

Posted on October 17, 2015 at 20:35

Read section 13.9.3 in RM0090, the F4 Reference Manual.

For your example, ADC1 sampling is complete after 3 cycles. Rerouting the multiplexer switch takes a minimum of 2 cycles, which is why a 5 cycle or longer delay is needed for ADC1 to start ADC2 sampling. Both ADCs convert for 12 cycles after sampling is complete, ADC1 completing first. The two conversion results are stored in the ADC_CDR 32-bit register. If you are using DMA, the two stored results are transferred to a 32 bit memory buffer by DMA after ADC2 has completed conversion. Conversion continues in this manner staggered by 5 cycles. Cheers, Hal

[adithya]

Posted on November 01, 2015 at 08:16

The DELAY is between two successive ADC CONVERSIONS(EOCs) not SAMPLING,meaning the time interval between the availability of the ADC value converted by ADC1 and the availability of the ADC value converted by ADC2 will be ''DELAY'' ADC clock cycles. It is only logical to set the delay to be greater than the sampling time because otherwise the ADC2's sampling phase will try to overlap with ADC1's sampling phase.THIS is where your DELAY will be set to SAMPLING_TIME+ whatever clk cycles. You get the delay that you want if you take care not to set the sampling time to be greater than the DELAY. Looking up to the supported sampling times(refer datasheet) and the supported DELAY values(5 to 20), you would do well to choose a combination that doesn't bring up the confusion in the first place.I don't know why someone would choose interleaved mode and use a sampling time of 28 clock cycles or more(I'd like to know),in which case even setting the DELAY to a maximum of 20 will not give you a straight forward DELAY value. 

In your case,the sampling time is 3 cycles and the DELAY is 5 cycles. Since the sampling time is lesser than the DELAY,you get what you want.The conversion of an analog value to a n-bit digital representation takes 'n' ADC clock cycles.Let t be the time represented in units of ADC CLK cycles.At, t=0 ADC1 starts sampling. t=3 ADC1 finishes sampling and starts conversion. t=(3+'n') ADC1 finishes conversion. Meanwhile,At,t=(3+'n'+5) ADC2 should have finished conversion.t=(3+'n'+5-'n') ADC2 would have finished sampling and started conversion.t=(3+'n'+5-'n'-3) ADC2 would have started sampling.You can substitute for different supported values for 'n' and get a sense of the timing. I will do it for n=12.At, t=0 ADC1 starts sampling. t=3 ADC1 finishes sampling. t=15 ADC1 finishes conversion. Meanwhile,At,t=(3+12+5)=20 ADC2 should have finished conversion.t=(3+12+5-12)=8 ADC2 would have finished sampling.t=(3+12+5-12-3)=5 ADC2 would have started sampling.Reorganizing 'em, t=0 ADC1 starts sampling. t=3 ADC1 finishes sampling and starts conversion. t=5 ADC2 starts sampling. t=8 ADC2 finishes sampling and starts conversion. t=15 ADC1 finishes conversion. t=20 ADC2 finishes conversion.20-15=5. Get the DELAY? Hope it helps :)