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matic
matic
Associate III
October 2, 2015
Question

2x DMA vs. 1x DMA

  • October 2, 2015
  • 8 replies
  • 2073 views
Posted on October 02, 2015 at 21:16

Some of the MCUs have 2 DMAs (12 channels), while others have 1 DMA (7 channels). What are benefits of 2 DMAs, except number of channels? Do DMA1 and DMA2 (in case of two DMAs) share the same bus, or do they have separate buses?

I'm asking for STM32F3 Series.

#dma
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8 replies

Tesla DeLorean
Tesla DeLorean
Guru
October 2, 2015
Posted on October 02, 2015 at 21:27

Depends on the specific part you're talking about. The F2/F4 associate DMA1/DMA2 with APB1/APB2 and the peripherals and triggers on each. ie USART1/6 are on APB2, they use DMA2. This should be readily apparent from the tables on the reference manuals, and the bus matrix diagram.

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matic
maticAuthor
Associate III
October 2, 2015
Posted on October 02, 2015 at 22:25

I'm talking about F3 Series. If you open RM (http://www.st.com/st-web-ui/static/active/en/resource/technical/document/reference_manual/DM00043574.pdf) at page 264, you can see DMA block diagram. I am not very familiar with hardware.

Does ''two DMAs'' mean that, the data could be transferred in parallel on DMA1 and DMA2 controller (channel 1 on DMA1 and channel 1 on DMA2 at the same time)?

Tesla DeLorean
Tesla DeLorean
Guru
October 2, 2015
Posted on October 03, 2015 at 00:19

On the F3 it just adds more channels, on more advanced devices.

Not sure ''parallel'' is exactly how I would characterize it. The bus matrix should permit certain transfers to occur without contending other bus usage, when contention occurs the utilization is sequenced between the parties, so all ultimately complete, in a order determined by timing, and priority of the requests. The part should be able to have ALL channels on ALL DMA units active at the same time, you're then only limited by the available bandwidth.

The F3 has CCM memory which is visible on the code and data buses of the processor, this can run code without contention from DMA

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matic
maticAuthor
Associate III
October 3, 2015
Posted on October 03, 2015 at 06:59

Thanks. Just one more thing.

In older design (MCU with 1 DMA - 7 channels ) I used ADC1 and ADC2 in dual mode with one DMA channel (channel 1). Now I go on STM32F303CB which has 2 DMA (7+5 channels). But ADC1 is on DMA1, while ADC2 is on DMA2 (same for ADC3 and ADC4).

Would be possible then to configure ADC1 and ADC2 in dual mode, because they don't share the same DMA? Probably I will have to switch ADC1 for ADC 3 or 4, because they share same DMA as ADC2.

Amel NASRI
Amel NASRI
ST Technical Moderator
October 7, 2015
Posted on October 07, 2015 at 16:56

Hi obid.matic,

When you are in dual mode, it is possible to read data with DMA in 2 ways:

1- Using 2 DMA channels (one for the master and another one for the slave)

2- Use only one DMA channel (the Master's one) and leave another one free. It is called the MDMA mode. In this case, data is read from the common ADC register.

You can refer to the ADC chapter in RM0316 for more details.

-Mayla-

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matic
maticAuthor
Associate III
October 7, 2015
Posted on October 07, 2015 at 19:12

Thanks Mayla.

So, in terms of speed, there is no advantage to use two separate DMAs (1 for master, 1 for slave) compared to MDMA mode?

I am still not sure, if I have ADC1 and ADC2 in MDMA mode (on DMA1)  and ADC3 on DMA2, if both DMAs can write at the same time. 

Tesla DeLorean
Tesla DeLorean
Guru
October 7, 2015
Posted on October 07, 2015 at 19:22

I've definitely posted a QUAD channel example, where the ADC are paired together in DUAL, and use their respective DMA. Managed to do so with a logical reading of the manuals.

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jpeacock
jpeacock
Associate
October 7, 2015
Posted on October 07, 2015 at 23:01

The 'F3 is a low cost part so it doesn't have the memory partitioning to really take advantage of parallel DMA on two channels.  The F2 and F4 have multiple SRAM regions with separate bus matrix ports so the two DMAs can run in parallel with the CPU if you are careful. 

The F3 only has one SRAM port so the DMAs will collide if both are running at the same time.  Now if you are using flash as a DMA source on one controller and SRAM as the source or target on the other you could overlap transfers through the bus switch.  Useful in special circumstances, like generating a DAC waveform from a flash table.

Otherwise the primary benefit is being able to set up more DMA channels even if they don't overlap.  It's very similar to an 'F1 DMA usage.

  Jack Peacock
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