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Is the STM32G431CBT6 LQFP48 compatible with STM32G431CBU6 UFQFPN48?

Peter Lissenburg
Associate III

I have a custom board based upon the B-G431B-ESC1. Using the LQFP48 foot print version of the same chip. It is missing a few pins, but my project is not using them.

After creating a new project using STM32G431CBT6 and the importing the original from MC workbench, I have 2 faults showing on CubeMX.
ADC1 and ADC2 Clock Prescaler cannot use clock div1
I choose div4 as I can't see anything in the data sheets to exclude div1 and MX proceeds to generate the code. After loading the project into CubeIDE, I change the div4 to div1 and all compiles fine.

Why does Cube MX create these errors? Is there an incompatibility?
Thank you for any insight into this.
Kind Regards.
P

1 ACCEPTED SOLUTION

Accepted Solutions
TDK
Guru

Glad you got it solved. Thanks for reporting back with the error explanation.

If you feel a post has answered your question, please click "Accept as Solution".

View solution in original post

4 REPLIES 4
raptorhal2
Lead

The data sheet will tell you they are pin, flash, RAM, peripherals and temperature compatible.

ST will probably find a Cube bug for this one.

TDK
Guru

Both of those chips will have the same clock restrictions. What does CubeMX say is the issue? Hover over the error to see. A screenshot of your clock config screen would be informative.

If you feel a post has answered your question, please click "Accept as Solution".
Peter Lissenburg
Associate III

Hi @TDK and @raptorhal2 ,

thank you for your replies, and TDK thanks for the prompt to check the clock config.

Here is the error.

STM32G431CBT6 MX ADC clock prescale error.jpg

And the clock config of the original STM32G431CBU6 clock config screen as generated by MC workbench.

original STM32G431CBU6 clock config screen.jpg

 And the STM32G431CBT6 clock config screen after Import with errors

STM32G431CBT6 clock config screen after Import with errors.jpg

 Here I eventually noted the PLL Source Mux has HSI selected instead of HSE, and that, and here is the direct reference to ADC, ADC12 Clock Mux is set to SYSCLK and not PLLP.

Correcting these and the PLL divider section allow selection of DIV1 in the ADC prescaler setup.

Thank you very much for the prompt, I made the silly assumption that the clock setup would be imported with the project. But it is not changed from the initial new project settings. Feeding 42.5MHz to the ADC is going to be better than 170MHz!

I have also learnt more about CubeMX.

Thank you, Cheers. P

TDK
Guru

Glad you got it solved. Thanks for reporting back with the error explanation.

If you feel a post has answered your question, please click "Accept as Solution".