cancel
Showing results for 
Search instead for 
Did you mean: 

Using USB OTG_HS in STM32F730R8

SVark.15
Associate

STM32F730R8 has embedded USB OTG_HS peripheral and internal FS OTG PHY support. What are the register settings required to run USB FS on the OTG_HS peripheral? What should be the system clock settings?

2 REPLIES 2
Uwe Bonnes
Principal III

What does the reference maual tell? Did you look for Cube examples?

The reference manual RM0431 doesn't have 'OTG high-speed block diagram for STM32F730R8' and hence it's not clear if it follows block diagram for STM32F7x2xx or STM32F7x3xx. The manual elsewhere speaks of 64 pin device having both FS PHY and ULPI interface. The clock tree (Fig.14, page 130) shows three USB clocks: (a) USB & RNG clock derived from PLL48CLK, (b) USB OTG HS clock derived from PLL1 & PLL2, (c) USBHS ULPI clock derived from OTG_HS_ULPI_CK. As I need FS PHY, I am not interested in ULPI clock. STM32F730R8 doesn't have PLL1 and PLL2; therefore HS clock cannot be generated. This puts me in a dock. Hence the question. Hope you can guide me with this clarification.