stm32n6 PPS in (ETH_PTP_AUX_TS)

[Noam_h]

Hello,

I need to sync the stm32n6 system timer to be used as PTP master. According to the Reference Manual there is a PPS input that can generate timestamp and interrupt: 

ETH_PTP_AUX_TS

But according to the RM it is not in all models, and I can't find which models it exists and how to map it to external IO.

Thanks,

Noam.

[FBL]

Hi @Noam_h 

I assume ETH_PTP_AUX_TS are missing in STM32N6 datasheet. I will come back to you  ASAP.

[Noam_h]

Thanks for the replay, ETH_PTP_AUX_TS is missing in the datasheet, and I couldn't find it in STM32cubeMX.

Thanks,

Noam.

[Noam_h]

Hi @FBL 

When do you think you can answer the question? 

We are in the process of Hardware design and it is critical to know which pin to connect. 

Thanks,

Noam.

[FBL]

Hi @Noam_h 

The issue is being tracked internally, and I cannot commit to a specific timeline officially for a valid pin.

[Noam_h]

Hi @FBL

while I am waiting, can I use one of the internal eth_ptp_trig[3:0] as an input and one of the timers with PPS trigger in and a trigger out connected to the eth_ptp_trig? 

If so, the routing from the trigger out to eth_ptp_trig is also not documented.

Thanks,

Noam.

[Noam_h]

Hello @FBL ,

Any news,regarding the issue?

Tganks,

Noam

[FBL]

Hello  @Noam_h 

Yes, on STM32N6 you can use an internal trigger as the PTP auxiliary timestamp source: a timer can take your PPS on one of its inputs and generate a trigger output, which is then internally routed to the Ethernet PTP auxiliary snapshot engine.

However, the internal routing  is not yet explicitly documented in the public RM. I’m currently waiting for official confirmation on this mapping so that it can be clearly documented (via RM update and/or errata), and so that we can reference it confidently in designs. Internal ticket number CDM0060329 for internal use.

[FBL · Accepted solution]

Hi @Noam_h 

I got the confirmation. You can sync the STM32N6 with internal signal connected to timer output trigger as I mentioned earlier. Here is the mapping to be added in reference manual :
 ptp_aux_ts_trig_i[0] (eth_ptp_trig0) connected internally with tim2_trgo
 ptp_aux_ts_trig_i[1] (eth_ptp_trig1) connected internally with tim3_trgo
 ptp_aux_ts_trig_i[2] (eth_ptp_trig2) not connected
 ptp_aux_ts_trig_i[3] (eth_ptp_trig3) connected internally with fdcan1_tmp

[Noam_h]

Thanks @FBL,

what about the  ETH_PTP_AUX_TS?

Thanks,

Noam.