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stm32f407 - timer10 interrupt handler called with delay

PLang.4
Associate II

Dear ST community,

I am running stm32f4-7 with FreeRTOS, and lwip, I am running TCP server by use of LWIP and some other application logic.

I need to generate PPM signal (8 PWM pulses with different length) every 20ms. For this purpose I am using timer10, and on each interrupt I set one GPIO pin to 1 or 0. Each PWM pulse is from 0,5ms to 1,1ms, so the timming i gues is not that fast... I am running system clock of 168MHz.

everything runs fine, just sometimes, PPM signal has some parts longer than it should be, most porbably timer interrupt is called with some delay. I suggest processor is bussy with some other task, thus cannot service interrupt for the timer. I have nested interrupts enabled with the priority for my timer = 0.

0693W000008FzzRQAS.png 

I was trying to debug this by SWV. where I can see entering and exiting of interrupts.

my question fot the SWV:

  1. What does the overflow means in the sequence list of exceptions?
  2. The message with index 55403 says I am entering TIM10 interrupt, but then I see index 55409 USART1_IRQ, however usart has lower priority than time10, so does this mean usart is preepting handling of tim10?
  3. index 55403 and 55417 I can see just tim10 entering, but no exit, why does it happen? most of the tiem I can see entering of tim10 interrupt and then exit of tim10 interrupt

0693W000008G01NQAS.png 0693W000008G01xQAC.pngQ1:

I know RTOS has probably heigher interrupt priority then timers do, so maybe when there is a flag raised for tim10 interrupt, it cannot be handled becouse RTOS is bussy with CPU, but I am delayed with interrupt routine for timer 10 for more then 0,1ms, which I thing is too much to be delayed even if RTOS is doing something. Or is it something that is normal?

Q2: Is there some other way to generate PPM signal?

Thank You.

Peter

1 REPLY 1
KnarfB
Principal III

I would generate the pulse train with a hardware timer (TIM) channel OC (output compare) feature combined with DMA. If you have 8 ppm channels you have 16 edges per 20 ms (?) round. Let the timer run at 1 MHz. Then you store the 16 edge-to-edge timings in the array and let the DMA be triggered by the timers OC event (not interrupt). The DMA target is th timer channels compare register for the next edge. After setup, this runs all in hardware without a single interrupt...