Posted on August 31, 2016 at 13:30Hi Mike xx,
The reason is that you do not want to mix your long running (upto 500ms)-low priority control transactions with your fast running-high priority transactions. Note that the problem is not that you do not service your high priority transactions first. The problem with using just one level of interrupt is that if you start a long running transaction, you cannot handle any high priority transaction that come in after until you are done with the long running transaction.
The ISR does not need to service all pending end points in one call. In fact a good design for the CTR_HP is to get the highest priority pipe from the hardware register (with no testing), clear pending for it, service it, and then exit (no looping). This optimizes the normal case of having only one high priority pipe pending. This also removes all interactions with the low priority pipes.
Note that, In our STM32F102/103 devices, USB events can generate 3 interrupts and are mapped to three different lines of the NVIC:
1) USB low-priority interrupt (Channel 20): Triggered by all USB events (Correct transfer, USB reset, etc.). The firmware has to check the interrupt source before serving the interrupt.
2) USB high-priority interrupt (Channel 19): Triggered only by a correct transfer event for isochronous and double-buffer bulk transfer to reach the highest possible transfer rate.
3) USB wakeup interrupt (Channel 42): Triggered by the wakeup event from the USB Suspend mode.
Take also the following note from the reference manual:
''The CTR bit is set by the hardware as soon as an endpoint successfully completes a transaction, generating a generic interrupt request if the corresponding bit in USB_CNTR is set.
An endpoint dedicated interrupt condition is activated independently from the CTRM bit in the USB_CNTR register. Both interrupt conditions remain active until software clears the pending bit in the corresponding USB_EPnR register (the CTR bit is actually a read only bit).''
-Hannibal-
Given that in some instances both interrupts can be active at the same time, what is the point or use in having two?
Is there any reason why the vector table for both shouldn't point to the same interrupt routine such that both interrupt sources can be cleared?.
I am not new to USB and its protocols but I am new to the STM32F1 implementation. What am I missing here?
