How to properly change sysclk frequency in STM32L0

[msemegen]

Hi,

I'm trying to dynamically change sysclk frequency in STM32L011xx. It's quite easy for STM32L4. All steps are described in detail in RM for L4 (here is what I extracted from RM: https://pastebin.com/KcCZNGAr) - my implementation here: https://github.com/msemegen/CML/blob/master/lib/hal/stm32l452xx/mcu.cpp.

Is there any detailed description for L0?

I found description how to change flash latency in the same voltage (RM 3.3.3, page 68) and how to change voltage range (RM 6.1.7, page 138). But no idea how change frequency, flash latency and voltage range together.

[Tesla DeLorean]

You understand that multiple load/stores against the same register are inefficient, right? Compilers won't fold access to volatile variables.

You can change the wait-states after you change to a lower speed, and before to a higher speed (FLASH_ACR). Again don't do this clear and set nonsense, read the current value, mask the bits, and set the new bits in a single operation. ie z = (z & x) | y;

To be honest the CM0 designs suffer very badly with a single wait state, you have to clock significantly faster to overcome the drag. ie if you can run at 24 MHz with zero, you probably won't improve much until you hit 37 MHz with one. Benchmark your code to check actual ramifications.

Consider running from RAM

The SysTick you're going to have to change the count to accomodate a different clock speed (RELOAD). Might consider changing speed in the SysTick interrupt to maintain continuity of the timeline.

[msemegen]

"You understand that multiple load/stores against the same register are inefficient, right? Compilers won't fold access to volatile variables."

Yes I'm aware of that, will be fixed 🙂

So, steps for speed increase are:

1. Change voltage scaling
2. Change flash latency
3. Change sysclk freq

And for decrease:

1. Change sysclk freq
2. Change flash latency
3. Change voltage scaling

Is that ok?