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F446RE HAL_SPI_TransmitReceive_DMA Difficulty; Transmit & Receive work; TransmitReceive doesn't

Associate II


I am using CubeMx and CubeIde to configure and test software.

I am using 2 Nucleo-F446RE boards back to back.  I am attempting to use HAL_SPI_TransmitReceive_DMA for transactions.   I use CubeMX to set up both boards and take the defaults.   One is setup as SPI_Master, the other is SPI_Slave.  I have implemented the necessary callback functions on both


On the  Master  I  use HAL_SPI_Transmit_DMA( ..).  On the Slave I use HAL_SPI_Receive DMA(..).  This works well.

On the Master I use HAL_SPI_Receive_DMA(....).  On the Slave I use HAL_SPI_Transmit_DMA( ..).  This also works well

On the Master I use HAL_SPI_TransmitReceive_DMA(..).  on the Slave I use HAL_SPI_TransmitReceive_DMA(..).   This doesn't work.  Only the first 3 characters are being received by the respective unit. The logic analyzer indicated the proper data is put on he MOSI line but only the first 3 characters are present of the MISO line.


More Details:

In all transactions I have implemented the RxCmplt, TxCmplt, TxRxCmplt callbacks and disabled the half buffer callbacks.  All of the Callbacks work as advertised.

The used CubeMx to set up the master and enables the hardware NSS.  I wanted HAL to manage the hardware.  The logic analyzer indicated that the NSS signal was never set by the software.  I had to implement the NSS signal in my software. After a lot of fussing I started to implementing Transmit and Receive as separate transactions. 

The Master receive, Slave transmit transaction worked without incident.

The Master transmit, Slave Receive had a slight problem.  The Slave always received  a 0 ('\0') as the first character.  The remaining of the received buffer contained the information sent by the Master.  The logic analyzer showed that there was no leading 0 in the MOSI data stream.  I solved this problem by inserting a few NOPs between setting the ENABLE line and HAL_SPI_Receive_DMA(..) call.  After that, all went well. Per the logic analyzer, it appears there needs to be a slight delay between setting the enable line and the beginning of the clock.  About 3 nops seem to work.


The MASTER trasnsmitreceive.. Slave transmitreceive...   The logic analyzer indicates that the proper data is present in the MOSI line but the Slave receiving buffer contains only the first 3 charactrers, the remaining characters are random characters. The MISO line  of the logic analyzer shows that only the first 3 characters of the Slave message are present.  The receiving buffer in the Master contains the data as display be the logic analyzer.

I can live with handling separate transmit/receive transactions for the current application but would  like to resolve the problem for future applications.

Any suggestions.