Bank filter confinguration working ramdonly with HAL_CAN over STM32L4

[Eugenia Suarez]

Posted on March 20, 2017 at 18:28

Working with HAL_CAN over STM32L4 polatform and kvaser (can analyzer).

I have this functions implementing my bank filtering:

void DRV_CAN_configureFiltersBank(void)

{ HCANFilter_Struct.FilterNumber = 0; //0 - 27 HCANFilter_Struct.FilterMode = CAN_FILTERMODE_IDMASK; HCANFilter_Struct.FilterScale = CAN_FILTERSCALE_32BIT; /*iid mask = 0...0 --> 0=don't care --> se acepta id con cualquier valor de bit en ese lugar*/ HCANFilter_Struct.FilterIdHigh = 0x0000; //11-bit ID in top bits ;//MSB of 32b config HCANFilter_Struct.FilterIdLow = 0x1F;//LSB of 32b config HCANFilter_Struct.FilterMaskIdHigh = 0x0000; //MSB HCANFilter_Struct.FilterMaskIdLow = 0x11; //LSB HCANFilter_Struct.FilterFIFOAssignment = 0; HCANFilter_Struct.FilterActivation = ENABLE; HCANFilter_Struct.BankNumber = 13; if (HAL_CAN_ConfigFilter(&HCAN_Struct,&HCANFilter_Struct) != HAL_OK) { DrvCan_Error_Handler(); } }

I would like to remark black letters. Since I have this configuration and I'm sending frames with different ID values and controller seems to get sometimes expected frames ID, but sometimes get non expected ones. Even sometimes ahs blocked correct IDs. If I understand correctly, with this configuration I have: 

• 0x0000001F = ID value = 11111
• 0x00000011 = mask value = 10001
• That means all ID numbers with 1xxx1 bits at the same position will pass, but if first 1 or last one is not present that frame will not entering to my FIFO.

Is it?

The thing is that I send a frame with 10100 = ID, but this frame passes the filters and it is processed (with an eco transmition after being receiving).

Is something wrong at my configuration understanding?

Thanks in advance.

#mask #id-filters #hal_can_receive_it #can #can-filter

[Tesla DeLorean]

Posted on March 20, 2017 at 21:02

X & 10001 will never equal 11111

X & 11111 can equal 10001

Remember what the mask is describing

[Tesla DeLorean]

Posted on March 20, 2017 at 21:05

HCANFilter_Struct.FilterIdHigh = ID << 5; //11-bit ID in top bits ;//MSB of 32b config

HCANFilter_Struct.FilterIdLow = 0;//LSB of 32b configHCANFilter_Struct.FilterMaskIdHigh = 0x7FF << 5; //MSBHCANFilter_Struct.FilterMaskIdLow = 0; //LSB

[Tesla DeLorean]

Posted on March 20, 2017 at 21:21

https://community.st.com/0D50X00009XkfSlSAJ

 

[Eugenia Suarez]

Posted on March 22, 2017 at 09:48

They are not equal, for sure, but I understood from datasheet, that when bit = 1, bit must match (the bit operates with &), but when 0 bit, it 'doesn't care'. So 1xxx1 could be from 10001 to 11111 codes that passes the filter bank. That's what specs are saying in the document. 

[Eugenia Suarez]

Posted on March 22, 2017 at 10:15

Thanks for the link, I will follow the example and instructions. I will comment the results! 

[Tesla DeLorean]

Posted on March 22, 2017 at 11:20

To restate, you have your logic backward and you are looking at the wrong bits.

[Eugenia Suarez]

Posted on March 22, 2017 at 12:15

Hi Clive, I have the same configuration of the link you passedand as expected, it works.

Thanks.

[lorenzo meneghello]

Posted on April 26, 2017 at 17:48

But why there's a shift of 5 if the register start from 0?

16bit: CAN_FxR1[15:8] + CAN_FxR1[7:0]

why it can work only with CAN_ID<<5?

Thanks

[Tesla DeLorean]

Posted on April 26, 2017 at 18:44

Look, because the STID is in the TOP 11-bits of the register, and the data on the wire is filling the most significant bits first, moving Left-to-Right on the diagrams