Hello Community,
We are using an STM32U595ZJT6Q microcontroller and have connected an MB85R4M2TFN-G-JAE2 FRAM via a parallel interface. The setup works well under normal operation and even after a power cycle — all data is retained and verified correctly.
However, we are facing a consistent issue when performing a microcontroller reset (MRST) without power cycling the board:
- After MRST, the data at address 0x00 in FRAM is found to be corrupted (0xFF).
- All other memory locations remain intact.
- This issue does not occur on power reset — only on MRST.
- We observed that CS & WR pins go low for ~300 ns during MRST, which seems to be the trigger.
Below is waveform captured for the mentioned behaviour.
Below things we did so far:-
- Added pull-up resistors on CS and WR line.
- Ensured early GPIO initialization in firmware to set FRAM control lines high.
- Verified that no write operations are performed in startup code.
- Checked FMC configuration and ensured no early access to FRAM.
- We observed this even when the controller flash is fully erased (No application code).
Despite all this, the issue persists — only address 0x00 gets overwritten with 0XFF after MRST.
It seems that on WARM reboot (keeping controller powered on) causes all GPIO pins to go LOW for approx. 5ns and 300ns rise time.
Has anyone encountered a similar issue with STM32 and parallel FRAMs? Are there any recommended hardware-level protections (e.g., latches, buffers, reset supervisors) or STM32-specific configurations to prevent this?
Any insights or suggestions would be greatly appreciated!
Thanks
Sushant Patil
