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VNF9Q20F Grounding

TH3221
Associate III

From the application schematics of VNF9Q20F, seperating my ground planes for CReg and DVcc but wouldnt DEV_GND (straight from the VNF9Q20F at the bottom) be connected as well instead of to battery ground? Shown as the drawn orange connection. Or both?

 

DEV_GND.png

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What you expect ? New physics ? Something working without solid gnd level , as good as possible ?

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3 REPLIES 3
AScha.3
Chief III

Because from ds :

AScha3_0-1717949081223.png

you should connect pin17 to ground plane , same as the cpu. And to (car) gnd(chassis) of course. 

Separating ground plane is no good idea, except for low noise analog circuits. (you dont have here - right?)

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TH3221
Associate III

Your right no low noise analog circuits, unless I would assume this chip would have something like that built in like for the current sense maybe? I just am trying to figure out why they would have separate grounds in the application schematic then?

You can see GND and DEV_GND? I've read the datasheet over and over and didn't see a reference to it

What you expect ? New physics ? Something working without solid gnd level , as good as possible ?

If you feel a post has answered your question, please click "Accept as Solution".