Last week, I have been testing SRK1000A in EVLSRK1000A-PF, in an application with 250 kHz fixed frequency flyback PWM with primary side control.
1. I struggled around the gate no longer driven in CCM-mode, and even in DCM upon more than moderate load. Finally, I found this sentence in section 6.5 of the data sheet:
When the VDS voltage gets higher than VR, the comparator triggers and the blanking time is terminated. This helps during constant voltage regulation operation, at high input voltage levels (where typically the conduction time of the primary MOSFET is short), avoiding that the blanking time determined by TOFF_min might delay the SR MOSFET turn-on. The internal threshold VR is fixed to 2.83 VCC [...]
A threshold like this is not given in the table to Electrical characteristics. If it would be present there, I could have been attended on it earlier. I was quite surprised that this device doesn't offer a bit more sophisticated recognition of the next PWM cycle in order to terminate a minimum t_off phase than a dumb voltage level. This requires one to design the transformer such that the PWM duty is quite low to ensure a higher secondary voltage at the instance that the primary MOSFET is on (not suitable at all for wide input range designs). Otherwise, I had to opt for the SRK1000 (without suffix). But its minimum t_off time of 280 ns is regarded as too low for robust operation.
2. Actually, if operating correctly at less than moderate load, I observed some time jitter at the moment that inductance energy has depleted and the usual ringing starts: up to 200 ns jitter in the adaptive timer off-timing, probably induced in conjunction with the voltage control loop, which could probably be rid of by modifying the compensation network of the feedback loop.
