Posted on May 17, 2011 at 09:53I have written a bootloader program using IAR 5.11 WorkBench for STR912FAW44 (ARM9 CPU) based 32 bit MCU and could load that program in Bank0 (512K Flash) and could debug that program through IAR Debugger.
Then I thought ok my program is now working using Bank0, I thought why not I run the same bootloader program into Bank1 and then switch to bank0 later part.
I was told by someone who worked on similar issue that Bootladers on Bank1 cannot run in debug mode. It has to run in release mode.
Using JlinkSTR91.exe I tried to set the Bank1 to be the boot bank. Then I tried to download the released version of the bootloader using FlashLoaderSTR91.out file. But my bootloader doesn't work at all.
What is the issue with respect to why my bootloader is not coming up and running, when the same code is running in bank0 in debug mode?
This is very very crucial project for me. Please do help me in resolving this issue immediately.
Also very clearly clearly for IAR 5.11 what steps I really need to do to switch from Bank1 to Bank0 where the User Application also do have Interrupts?
Since Iam using 5.11 the linker file should be like STR91x_FLASH but not like lnkarm_flash.xcl in 4.41,4.42 etc.
Part of 91x_init.s is
Also uncomment the #Boot_Bank_1, comment #debug in 91x_conf.h and comment the #if debug debug() #endif in main.c()
#ifdef BUFFERED_Mode
; BUFFERED_Mode
; ------------------------------------------------------------------------------
; Description : Enable the Buffered mode.
; Just enable the buffered define on the 91x_conf.h
;
http://www.arm.com/pdfs/DDI0164A_966E_S.pdf
; ------------------------------------------------------------------------------
MRC p15, 0, r0, c1, c0, 0 ; Read CP15 register 1 into r0
ORR r0, r0, #0x8 ; Enable Write Buffer on AHB
MCR p15, 0, r0, c1, c0, 0 ; Write CP15 register 1
#endif
LDR R6, =0x54000004 ; non boot bank size
LDR R7, =0x6 ; 512K
STR R7, [R6]
LDR R6, =0x5400000C ; boot bank address = Bank 1
LDR R7, =0x0 ; 0x0
STR R7, [R6]
LDR R6, =0x54000010 ; non boot bank address = Bank 0
LDR R7, =0x20000 ; 0x10000 = 4x 0x4000
STR R7, [R6]
LDR R6, =0x54000018 ; enable Non Boot bank
LDR R7, =0x18
STR R7, [R6]
