Posted on May 12, 2004 at 12:04You need to use the bres and bset instructions with care specially when you have a mixed port configuaration. It is recommented to use Logical OR , AND instructions. There is an FAQ in ST7 knowledgebase for this subject.
I add it for your reference:
Question: 467
Can read/modify/write operation be performed on DR registers?
Answer:
Some instructions like BSET,BRES work in following sequence. They read the register, modify the bit ( SET/RESET) and then write back to the register. When this operation is performed on ports ( DR register), some care should be taken because Read operation in the instruction can read the port pin instead of the register.Most of the ST7 IOs ( except 7265x) have a multiplexer on DR input. When a Read/modify/write is performed on IO port where all pins are configured as output ( open-drain or PP-out) there is no problem with BSET/BRES on DR register because read operation will read the DR register.In such a case full port should be configured as output. If the IOs have mixed configuration both input ( DDR=0) and output, then Read operation will read the pin instead of DR register if some pins are configured as input. The modify operation will correctly modify the desired bit and operation will write wrong value on DR for bit position configured as input. Later if this input pin is changed as output there will be wrong value on the pin . illustration: before BSET/BRES PADR = 0000 0000 PADDR = 0000 1111 PAOR = 0000 1111 suppose there are pull-ups configured at PADR bits 4,5,6,7 BSET PADR, 0 will have following sequence read operation will read1111 0000 internally modify BSET PADR.0 will cause 1111 0001 internally Write operation will write 1111 0001 on PADR. So, it can be noted that for the user PADR bits 4,5,6,7 got accidently changed . In case these pins are configured as output later-on, user is assuming a 0 on these pins but he will get the 1 on these pins which is wrong.
Work-around
----------------
If DR is written always before changing the IO from input configuration (DDR.x=0) to output(DDR.x=1) the problem will not appear. The work-around of this is us the RAM variable for port registers which are configured as both input and output and performe BSET/BRES in RAM and then write to DR register. Pls note that for 7265x this note is not valid an the problem can be seen with open-drain ports also. So, it is advice not to use BSET/BRES on the DR register unless care has been taken.
