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Debugging checkstop reset on SPC560P44

davedave95
Associate III
Posted on June 14, 2017 at 11:52

Hello,

Under certain circumstances involving high interrupt load the CPU triggers a checkstop reset, RGM_FES is 0x8008 in after reboot, indicating the F_CHECKSTOP bit is set.

How do I debug the source of the checkstop reset?

My plan was to disable checkstop reset by setting FERD.D_CHECKSTOP to 1, and then read out MCSR with the debugger when the CPU hits checkstop state. t seems that FERD.D_CHECKSTOP is read only though, so I have no way to disable the checkstop reset.

What would be the best way to debug the checkstop reason, and how can I inspect the value of MCSR before the CPU is forced through a reset?

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1 REPLY 1
Erwan YVIN
ST Employee
Posted on June 14, 2017 at 15:50

Hello Gert ,

Maybe you can enable FCCU. (cf Chapter 30)

Check chapter 30.7.9 for the Fault mapping

  

   Best regards

                

              Erwan