DMA register definitions for SPC560B54x, SSPC560B60x or SPC560B64x MCU family

[ext-daniel]

Posted on July 12, 2013 at 09:15

Hi,

I need to implement a DMA driver for one of the microprocessors from above but I did not find any suitable register definitions file within your example projects.1) Please indicate me where could I find that definition file(s).2) Is there any DMA example/stub driver for this kind of processor ?Best regards,Daniel #spc5studio

[Nickname16641_O]

Posted on July 12, 2013 at 14:20

Hi,

DMA driver support for SPC560Bxx will be introduced in version 1.2.0 which will be released in few weeks. If you cannot wait the new DMA driver you can take definitions from here: https://sourceforge.net/p/spc5-hal/code/250/tree/trunk/_code/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h Giovanni

[ext-daniel]

Posted on July 24, 2013 at 11:11

Hi Giovanni,

I would need a hint regarding DMA since everything seems to be set correctly set but when DMA with SPI starts, POPR register is read over and over again without the RX FIFO to be properly emptied as in a normal reading :ui8SPISlave_RxData = DSPI_0.POPR.R;        // read from SPI serial ( how many bytes )DSPI_0.SR.B.RFDF = 1;   /* clear RFDF flag */       The setting for DMA is :edmaChannelSetup(spip->rx_channel,            /* channel.                 */                   DSPI_POPR8_ADDRESS(spip),    /* src.                     */                   &datasink,                   /* dst.                     */                   0,                           /* soff, do not advance.    */                   0,                           /* doff, do not advance.    */                   0,                           /* ssize, 16 bits transfers.*/                   0,                           /* dsize, 16 bits transfers.*/                   1,                           /* nbytes, always one.      */                   n,                           /* iter.                    */                   0,                           /* slast.                   */                   0,                           /* dlast.                   */                   EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END);     /* mode.*/Best Regards,Daniel

[Nickname16641_O]

Posted on July 24, 2013 at 12:27

Hi,

The continuous triggering could be a problem with the DMA_MUX settings. Giovanni

[ext-daniel]

Posted on July 24, 2013 at 12:36

Hi,

There is no continuous triggering. My problem is that the RX FIFO does not get freed and DMA reads the same data and fills the destination buffer.Is it supposed that the clearing for RFDF is done automatically by the DMA module ?Best Regards,Daniel

[Nickname16641_O]

Posted on July 24, 2013 at 12:58

According to the reference manual the DMA clears that bit:

''Receive FIFO Drain Flag. The RFDF bit provides a method for the DSPI to request that entries be removed from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be cleared by writing 1 to it or by acknowledgement from the DMA controller when the RX FIFO is empty.'' It is possible that the DMA is not actually reading the register because it is not triggered, you should be able to verify this by examining the DMA TCD registers at runtime. Giovanni

[Luca RODESCHINI]

Posted on July 25, 2013 at 22:44

Hi,

SPC5studio revision 1.2 will be available for download in a few days. a new osek compliant os inside, more mcu supported, more sw examples; more configurable components Who download it previously will get automatically a mail with the notification of the new release and the link to download. luca