LIS3DH on a shared SPI bus

[JMatt]

I have an LIS3DH on a proprietary board using a BMD340. I am using the two inertial interrupts, I configure int1 to interrupt on any axis activity that exceeds threshold longer than duration. I don't latch the interrupt. I configure int2 to interrupt when all the axes have activity below threshold longer than duration. Also not latched.

This is working so I'm confident about my code. However, there is strange behavior. The LIS3DH shares the SPI bus with anther device. I have each device configured as separate SPI instances. They share the CLK, MOSI, and MISO lines from the BMD340. They have separate CS lines.

Strange behavior 1) I check the interrupt lines with my logic analyzer. When I trigger int1, I get a 450 uS pulse. The line goes high for 450 uS then back low. As expected. I check the interrupt line for int2. When I trigger int2, the interrupt line goes high and stays high for 95 mS before it goes low. That 95 mS is about the time it takes my interrupt service routine to do measurements using the LIS3DH. I can believe that the drop back low occurs around the time I stop using the SPI bus. Any ideas why int2's interrupt line stays high while int1's line doesn't?

For Interrupt 1:
start SPI to set up INT1
write 0x27 to CTRL_REG1      // 10 Hz ODR and using 12 bit
write 0x01 to CTRL_REG2      // High Pass filter for INT1 at 0.2 Hz cutoff
write 0x40 to CTRL_REG3      // IA1 goes out on pin 11
write 0x00 to CTRL_REG6      // Making sure its in default state
write 0x88 to CTRL_REG4      // 2g full scale and 12 bit
write 0x00 to CTRL_REG5      // No latch
write ox08 to INT1_THS       // 128mg threshold
write 0x02 to INT1_DURATION  // 2 sec INT1_DURATION
read REFERENCE               // Dummy read to setup the high pass filter
write 0x2a to INT1_CFG       // Use all axes high with OR logic
 stop spi
go about my business util interrupt
interrupt triggers start SPI, collect LIS3DH data, stop spi
 
For Interrupt2:
start SPI to setup INT2
write 0x27 to CTRL_REG1      // 10 Hz ODR and using 12 bit
write 0x02 to CTRL_REG2      // High Pass filter for INT2 at 0.2 Hz cutoff
write 0x00 to CTRL_REG3      // Making sure its in default state
write 0x20 to CTRL_REG6      // IA2 goes out on pin 9
write 0x88 to CTRL_REG4      // 2g full scale and 12 bit
write 0x00 to CTRL_REG5      // No latch
write ox08 to INT2_THS       // 128mg threshold
write 0x02 to INT2_DURATION  // 2 sec INT1_DURATION
read REFERENCE               // Dummy read to setup the high pass filter
write 0x95 to INT2_CFG       // Use all axes low with AND logic
Stop SPI
go about my business util interrupt
interrupt triggers start SPI, collect LIS3DH data, stop spi

Strange behavior 2) When I power up the board I can always do an interrupt 1 as shown above. My firm ware will hang if I try to do it a 2nd time. I can setup and trigger int2 as many times as I want. Debugging lead me to failure at writes to varying registers in the INT1 setup. Searching the web lead me to :

https://www.reddit.com/r/AskElectronics/comments/6g8osy/st_accelerometer_lis3dh_misbehaving/ and

https://community.st.com/s/question/0D50X00009XkXz9SAF/lis3dh-interrupt-int1-mode-not-firing

I'm thinking I have a SPI communications issue for my particular situation. the LIS3DH Data sheet states:

"Registers marked as Reserved or not listed in the table above must not be changed. Writing to those registers may cause permanent damage to the device."

Yet on page 22 of:

https://www.st.com/content/ccc/resource/technical/document/datasheet/24/b9/50/c5/61/ae/4d/58/DM00150114.pdf/files/DM00150114.pdf/jcr:content/translations/en.DM00150114.pdf ST states:

"Note: If the IIS328DQ is used in a multi-SPI slave environment (several devices sharing the same SPI bus), the accelerometer can be forced by software to remain in SPI mode. This objective can be achieved by sending at the beginning of the SPI communication the following sequence to the device: a = read(0x17) write(0x17, (0x80 OR a)) In this way, CTRL_REG4 is programmed to enhance the robustness of the SPI."

This fix was apparently also suggested for the LIS3DH in that zombie st community post listed above, I don't know if its a good idea to trust what I read on https://www.reddit.com/r/AskElectronics so I'm asking the ST community,

As with the LIS3DH, register 0x17 is reserved in the IIS328DQ, with the same warning about modifying it.

Can you tell me if I can safely modify the LIS3DH register 0x17 as suggested for the IIS328DQ ?

[Eleon BORLINI]

Hi @JMatt​ ,

it took some time for me to go through the question.

For the Point A) I see that you set the INT configuration in different way for INT1 compared to INT2. Is this OK to use the AND logic for your application purposes?

write 0x95 to INT2_CFG       // Use all axes low with AND logic

I think that for the INT2 condition to be well working there could be some logic issues, since if -for example- the LIS3DH is in flat position, you'll always read 1g value on Z axis, so that, depending on the threshold set (for example, 128mg), the risk is that the in general you'll never cross the low threshold at least on 1 axis.

For the Point B), although it is not officially suggested for the LIS3DH, you could implement the same trick of the IIS328DQ (but first save the content of the 17h register in case something goes wrong).

-Eleon