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Failure to get lock with TESEO-LIV3F

aracnoid149
Associate II

I have been attempting to get a GPS lock with the TESEO-LIV3F, and I am not able to.  I am fairly certain that it has to do with how I designed the signal chain from the chip antenna to the RF-IN pin on the LIV3.  I have ensured that it was outside with a clear view of the sky, I have sent the $PSTMCOLD, 6 command to it.  I have tried to initiate with this command; $PSTMINITGPS,3912.826,N,11939.993,W,1487,17,02,2026,21,11,30, but then later sent $PSTMRESTOREPAR to reset it.  I do not have teseo-studio seeing as I am on linux.  Any help will be appreciated.

GPS PCB.png

GPS schematic.png

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Accepted Solutions
aracnoid149
Associate II
 

futurama-good-news-everyone-2665645285.gif

I was able to get a lock.  After looking deeper into LNAs I found that the one I have on there already was fine, I just had the wrong value of inductor and capacitor on the RF in side of the LNA.  Originally I had L1 and C8 set to 5.6nH and 120pF respectively.  According to this datasheet, they needed to be 10nH and 1nF instead.  Once I replaced those parts, it worked perfectly.  

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5 REPLIES 5
GalaxyQuest
ST Employee

Hi,

Can you please tell me the antenna part # ?

I was also looking over the LNA and SAW filter being used.

Is the LNA, BGA123L4? According to datasheet for this part, found here, BGA123L4 Data Sheet , the LNA is for NSS L5/E5/G3/L2/E2 band applications (1164 to 1254 MHz) and not for L1.

LIV3F is an L1 GNSS device.

Can you try replacing the LNA?


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Well well well, the mismatched LNA might definately explain it.  Let me see if I can find an LNA with the same footprint but the correct band to replace it.  Also, my antenna is the H2U14W1H1A0400.  One more thing that just occured to me today is my impedence considerations.  When I was designing the PCB, I was using the impedance calculator on digikey, and the impedance dialectric value I plugged into it was 3.61 which I took off of Osh park's data for their 4 layer boards.  The calculator didn't have an option for 4 layer with the strip on top, so I used he micostrip selection and calculated for going from the top strip to the next layer of copper below.  Did I use it right or should I have calculated in a different way or will it make a significant difference?

 

 

 

The impedance is defined between 2 layers when the impedance line is on external layer. The external layer and the ground layer below the impedance area.

Then, microstrip model is the right one. And you need to use PCB thickness between top layer (where I think you route the 50ohms line) and the GND layer below the RF part. 


In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.
aracnoid149
Associate II
 

futurama-good-news-everyone-2665645285.gif

I was able to get a lock.  After looking deeper into LNAs I found that the one I have on there already was fine, I just had the wrong value of inductor and capacitor on the RF in side of the LNA.  Originally I had L1 and C8 set to 5.6nH and 120pF respectively.  According to this datasheet, they needed to be 10nH and 1nF instead.  Once I replaced those parts, it worked perfectly.  

Great job, glad you were able to resolve it


In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.