X-CUBE-AI Inference Issue: Int8 Model Always Predicts "Class 0" Regardless of Input Data

[NTUST_best_lab]

I am currently working on deploying a quantized Int8 TFLite model (ECG classification) onto the NUCLEO-N657X0-Q board using X-CUBE-AI.

The Issue: I have successfully flashed the FSBL, Application, and Model Weights . The system boots up, and the inference loop runs without errors. However, the model always predicts "Class 0" (Normal) , even when I feed it hardcoded input data that corresponds to "Class 1" (Abnormal).

The Problem: I performed a deep-dive debugging session by pre-filling the tensor arena (SRAM) with a garbage pattern (0x55) before every inference to check if the NPU is actually writing data.

My Findings:

1. Input Data: The input buffer is correctly updated for each sample (verified via printf).

2. Layer-by-Layer Failure:

   • Ep2 (MaxPool) & Ep5 (Logits): The memory at these output addresses remains 0x55 55 55.... This indicates the NPU failed to write to these SRAM addresses.

   • Ep3 (Gemm1): The output is static and does not change with input.

   • Ep4 (Gemm2): Surprisingly, this layer's output does change with input, suggesting the NPU has access to some memory regions but not others.

3. Final Output: Because the final Logits/Softmax layers are never written (reading garbage 0x55 or old data), the final prediction is always stuck at Class 0 (Normal).

System Configuration:

• Weights: Located in External Flash (0x71000000). Verified readable by CPU.

• SRAM: Model uses AXISRAM5 (around 0x342E0000) for activation buffers.

• Security State:

  • CPU: Secure / Privileged.

  • SAU: All regions configured as Secure.

• Cache: I am using mcu_cache_clean_invalidate_range (Input/Output) and npu_cache_invalidate extensively.

It strongly looks like a RIF (Resource Isolation Framework) or Bus Permission issue where the NPU (as a Master) is blocked from writing to specific offsets in AXISRAM5.

1. What is the correct RIF configuration for the NPU Master and SRAM Slaves on STM32N6 to allow full Read/Write access in a Secure-only environment?

2. Do I need to assign a specific CID (Compartment ID) to the NPU to allow it to write to these SRAM regions?

3. Are there any specific HAL_PWR settings required for the full NPU SRAM banks to be active?

Any advice on unlocking the NPU write permissions would be appreciated.

Although I've identified a possible problem, I'm not sure if it's caused by a configuration error in other parts.
Here is my code ,model, setting and the log for debug : https://github.com/tw13256/Try-to-put-a-model-on-the-NUCLEO-N657X0-Q-